JPH039057Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power failure processing circuit in a microcomputer application device.

[Conventional technology]

In the conventional power failure processing circuit, the configuration is shown in FIG. 1a and the operation is shown in FIG. At the same time as time T11), the monostable multivibrator circuit 10 that outputs a pulse for a certain period of time in response to the input is started, and the time until the power failure processing program of the central control unit completes operation (P1 =
At time T12-T11), to the reset circuit 12 that sends the reset signal RST to each part of this device,
AND function gate circuit 13 and OR function gate circuit 1 for power outage detection signal POW
It operates to prohibit input via 4. If the power failure detection signal POW continues after the prohibition time P1 determined by the constant pulse of the monostable multivibrator circuit 10 has elapsed, the reset circuit 12 is activated and the device is reset in preparation for re-operation after the power is restored. Even if the state is maintained and the power outage is restored and the power outage detection signal POW disappears (time T13), the reset signal continues to be sent for a certain period of time (P2 = time T14-T13) to ensure that the device restarts.

If the power is restored while the central control unit is processing a power outage, in order to prevent the power outage detection signal POW from disappearing and the reset circuit 12 not being activated, the reset circuit 12 is activated when the operation of the monostable multivibrator circuit 10 ends. A single pulse generation circuit 11 is provided which generates a short single pulse sufficient to activate the reset circuit, and the reset circuit 12 is automatically activated by the output signal of the circuit 11 to generate a single pulse that is short enough to activate the reset circuit.
During P2, a reset signal is sent to reset the device and restart operation.

The reset circuit 12 is an OR circuit as described above.
This circuit has the function of outputting a reset signal in response to the rise of the output signal of the functional gate circuit 14, and further outputting the reset signal for a certain period of time even if the output signal of the circuit 14 disappears, and is commonly used in microcomputer circuits. It can be configured with a manually operable reset circuit that is currently in use (for example,
(Refer to pages 48-49 of ``Illustrated Instructions for Using the Microcomputer Z-80,'' published by Ohmsha Co., Ltd. on May 20th).

[Problem that the invention attempts to solve]

In this way, the monostable multivibrator circuit 10 and the single-shot pulse generation circuit 11 are closely related to the power failure processing operation time of the central control unit, so precise adjustment confirmation is required for each unit, and single-shot pulse generation In order to ensure the minimum pulse width necessary for starting the reset circuit 12 for the circuit 11, it is necessary to adjust the circuit setting conditions for each unit, making it difficult to operate stably over a long period of time without maintenance. .

The purpose of the present invention is to activate the reset circuit in response to a signal from the central control unit indicating the end of the power failure handling operation, thereby making precise adjustments and setting the guard time during the power failure handling operation of the central control unit. The object of the present invention is to provide a power outage processing circuit that operates stably over a long period of time by eliminating circuits that require confirmation.

[Means for solving problems]

The power outage processing circuit of the present invention includes a first state holding circuit that holds a power outage detection signal from the power supply and inverts the output in response to an initialization reset signal from the central control unit; a first gate circuit that does not pass the detection signal in a held state but passes it in an inverted state; a second gate circuit that holds a power failure processing program end signal from the central control unit and inverts its output in response to the initialization reset signal; a state holding circuit; a second gate circuit output that ORs the output of this circuit and the output of the first gate circuit; and a circuit for transmitting the initialization reset signal activated by the output signal thereof; It is characterized by being configured.

〔Example〕

Referring to FIG. 2, one embodiment of the present invention includes a first state holding circuit 20, an AND function gate circuit (first gate circuit) 21, and an OR function gate circuit (second gate circuit) 22. and reset circuit 2
3 and a second state holding circuit 24.
Reset circuit 23 can be constructed of the same circuit as reset circuit 12 described in FIGS. 1a and 1b.

The operation when a power outage occurs will be described with reference to FIG. 3 as well. At time T1, when the power outage detection signal POW is input, the first state holding circuit 20
is held in This state holding circuit 20 sends an interrupt signal IRP to a central control unit (CPU, not shown) for starting a power outage processing program.
On the other hand, the output signal of the state holding circuit 20 is also sent to the AND function gate circuit 21 to inhibit the output of this circuit 21, and the power failure detection signal POW is input to the reset circuit 23 via the OR function gate circuit 22. prohibited. When the CPU finishes executing the power outage processing program and executes a predetermined command (OUT command, memory write command, etc.), the operation end signal END is input to the second state holding circuit 24 and held at time T2. . The output of this state holding circuit 24 is sent to the OR function gate circuit 22, and a signal obtained by performing a logical sum with the output signal of the previous AND function gate circuit 21 is sent to the reset circuit 23. As soon as this OR signal is input, the reset circuit 23 outputs the reset signal RST to the CPU.
Output to. (Time T2). Also, the reset signal
RST is the first and second state holding circuit 20, 2
Sent to 4. As a result, the power failure detection signal POW
While the prohibition condition of the AND function gate circuit 21 that had prohibited the
The reset circuit drive signal from . If the power outage continues when the reset circuit 23 is activated, the AND function gate circuit 21 and
Since the power failure detection signal POW is input to the reset circuit 23 through the OR gate circuit 22, the operation of the reset circuit 23 is extended until the power failure detection signal POW disappears (time T3), so the device remains in operation until the power is restored. Reset state is maintained (time T4).
That is, the reset signal output by the reset circuit 23 in response to the output of the OR function gate circuit 22
The minimum pulse width of RST is T=T4-T3, which has been determined to ensure re-operation of the device. Here, the reset circuit 23 starts operating when the output of the OR function gate circuit 22 is inverted (time T2) and begins to send out the reset signal RST, and even if the output of this circuit 22 is further inverted (time T3), the above-mentioned The reset signal RST is sent out for a certain period of time T. That is, in FIG. 3, the pulse from time T2 to T3 of the reset signal RST is an extended part of the operation of the reset circuit 23, and is the power failure detection signal.
The period from time T3 when POW disappears to time T4 is the above-mentioned original reset pulse width.

In addition, if the power outage continues without being restored, the fourth
As shown in the figure, each output signal decreases as the power supply voltage decreases (time T5), and when the voltage falls below the guaranteed operation voltage of each circuit, its operation is no longer guaranteed. In other words, after a power outage occurs, it operates normally with backup power until time T5, but at this time
After passing T5, the voltage of the backup power supply decreases and this state occurs. However, data required after the power is restored has already been backed up by the power outage processing program activated by the interrupt signal IRP. Thereafter, when the power supply voltage recovers to the voltage guaranteed for operation of each circuit, the device maintains the reset state until the power supply is completely restored.

In addition, as shown in FIG.
If the power supply has already been restored and the power failure detection signal has disappeared (time T6) when the reset circuit 23 is activated (time T2), the device starts operating after the reset circuit 23 has finished operating (time T2). T7). That is, the reset circuit 23 is the OR function gate circuit 2.
In response to the short pulse (time T2) output by the circuit 2, the reset signal RST of the above-mentioned minimum pulse width T (=T7-T2) is output.

Note that the second state holding circuit 24 is the CPU
The built-in status display signal output (for example, HLT command of 8080 series CPU) can be used instead as the operation end signal END, or the power failure detection signal POW can be directly transferred and used as the interrupt signal IRP. can be implemented.

[Effect of idea]

As explained above, according to the present invention, the power outage processing operation time of the central control unit is guaranteed by sending out a reset signal and instructing the restart of the operation in response to the end signal of the power outage processing operation from the central control unit. This eliminates the need for strict circuit adjustment, etc., and provides a power outage processing circuit that operates stably for a long period of time. Further, according to the present invention, the operable time of the power outage processing program is only affected by the output voltage holding time of the power supply, so that the power outage processing program can be easily changed and set.

[Brief explanation of the drawing]

FIG. 1a is a block diagram showing an example of a conventional power outage processing circuit, FIG. 1b is a time chart explaining the operation of FIG. 1, and FIG. 2 is a block diagram of an embodiment of the present invention.
Figure 3 is a time chart in the case where the power outage is restored midway in the same example, Figure 4 is a time chart in the case where the power outage continues in the same example, and Figure 5 is a time chart in the same example where the power is restored immediately after the power outage is detected. This is a time chart if you do. 20...first state holding circuit, 21...AND
Functional gate circuit, 22...OR functional gate circuit,
23...Reset circuit, 24...Second state holding circuit.

Claims (1)

[Scope of utility model registration request] a first state holding circuit that holds a power outage detection signal from the power supply and inverts its output in response to an initialization reset signal from the central control unit; the circuit is opened and closed by the output of this circuit to allow the power outage detection signal to pass in a held state; a first gate circuit that allows the signal to pass through in an inverted state; a second state holding circuit that holds the end signal of the power outage processing program from the central control unit and inverts the output in response to the initialization reset signal; and a second gate circuit that ORs the output of the second gate circuit and the output of the first gate circuit; and a circuit that sends out the initialization reset signal that is activated by the output signal of the second gate circuit. processing circuit.