JPH0392829U - - Google Patents
Info
- Publication number
- JPH0392829U JPH0392829U JP1990001511U JP151190U JPH0392829U JP H0392829 U JPH0392829 U JP H0392829U JP 1990001511 U JP1990001511 U JP 1990001511U JP 151190 U JP151190 U JP 151190U JP H0392829 U JPH0392829 U JP H0392829U
- Authority
- JP
- Japan
- Prior art keywords
- transfer gates
- changes
- level
- threshold value
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Pulse Circuits (AREA)
Description
第１図はこの考案の実施例を示すブロツク図、
第２図はそのトランスフアゲート２１のみがオン
状態の等価回路図、第３図はトランスフアゲート
２１及び２２のみがオンの状態の等価回路図、第
４図は出力バツフア２７の入力の立上りを示す図
、第５図は出力バツフア２７の出力の立上りを示
す図、第６図及び第７図はそれぞれ従来の可変遅
延回路の一部を示すブロツク図である。
Figure 1 is a block diagram showing an embodiment of this invention.
2 is an equivalent circuit diagram with only the transfer gate 21 in the on state, FIG. 3 is an equivalent circuit diagram with only the transfer gates 21 and 22 in the on state, and FIG. 4 is a diagram showing the rise of the input of the output buffer 27. , FIG. 5 is a diagram showing the rise of the output of the output buffer 27, and FIGS. 6 and 7 are block diagrams each showing a part of a conventional variable delay circuit.
Claims (1)
された複数のトランスフアゲートと、 これら複数のトランスフアゲートの他端に接続
され、入力がしきい値以下で第１レベルを出力端
子に出力し、しきい値以上で第２レベルを上記出
力端子に出力するしきい値回路とを有し、 上記複数のトランスフアゲートのオンの数を変
更して上記入力端子及び上記出力端子間の遅延量
を変更するようにしてなる可変遅延回路。[Claims for Utility Model Registration] A plurality of transfer gates whose one end is connected to an input terminal and are connected in parallel to each other, and a plurality of transfer gates which are connected to the other ends of the plurality of transfer gates and whose inputs are at a first level when the input is below a threshold value. and a threshold circuit that outputs a second level to the output terminal at a threshold value or higher, and changes the number of ON of the plurality of transfer gates to output the input terminal and the output terminal. A variable delay circuit that changes the amount of delay between terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990001511U JPH0392829U (en) | 1990-01-10 | 1990-01-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990001511U JPH0392829U (en) | 1990-01-10 | 1990-01-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0392829U true JPH0392829U (en) | 1991-09-20 |
Family
ID=31505415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990001511U Pending JPH0392829U (en) | 1990-01-10 | 1990-01-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0392829U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208114A (en) * | 1984-03-31 | 1985-10-19 | Toshiba Corp | Semiconductor integrated circuit device |
-
1990
- 1990-01-10 JP JP1990001511U patent/JPH0392829U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208114A (en) * | 1984-03-31 | 1985-10-19 | Toshiba Corp | Semiconductor integrated circuit device |
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