JPH0394832U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a logic signal amplification circuit according to the present invention, and FIG. 2 is a circuit diagram of an example of a similar circuit according to the prior art. In the figure, 10, 20...a pair of series circuits, 11, 21...
... Input transistor, 12, 22 ... Output transistor, 30 ... Equalization circuit, 31, 32 ... Transistor for shorting the signal line of output signal, 33 ... Inverter, 40 ... Control transistor, 50, 6
0... Conventional amplifier circuit, 51, 52, 61, 62
...Transistor, 53, 63...Current mirror circuit, 53f, 63f...Reference transistor, 53
r, 63r...driven transistor, E...ground point, EP...equalization pulse, Si...input signal,
... Complementary input signal, So ... Output signal, ...
Supplementary output signals, SS: control signal, Vd: power supply voltage.

Claims (1)

[Scope of utility model registration request] A circuit consisting of field-effect transistors that receives a pair of input signals representing complementary logic states and amplifies them into a pair of output signals representing complementary logic states, the circuit comprising an input transistor and an output of an opposite channel type. A pair of series circuits of transistors is provided, the potential at the interconnection point of the input transistor and output transistor of each series circuit is applied to the gate of the output transistor of the other series circuit, and an input signal is applied to the gate of the input transistor of each series circuit. A logic signal amplification circuit in which an output signal is derived from the interconnection point of an input transistor and an output transistor in each series circuit.