JPH02838U - - Google Patents
Info
- Publication number
- JPH02838U JPH02838U JP510988U JP510988U JPH02838U JP H02838 U JPH02838 U JP H02838U JP 510988 U JP510988 U JP 510988U JP 510988 U JP510988 U JP 510988U JP H02838 U JPH02838 U JP H02838U
- Authority
- JP
- Japan
- Prior art keywords
- mos
- driving
- signal
- fet
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案の信号出力回路を示す回路図、
第２図及び第３図は第１図の各部波形を示すタイ
ミングチヤートである。
８…センスアンプ、１８…制御回路、１９，２
０…Ｎ―ＭＯＳ、２１，２２…Ｐ―ＭＯＳ、２３
…共通バス。
FIG. 1 is a circuit diagram showing the signal output circuit of the present invention.
2 and 3 are timing charts showing waveforms of various parts in FIG. 1. 8...Sense amplifier, 18...Control circuit, 19,2
0...N-MOS, 21, 22...P-MOS, 23
…Common bus.
Claims (1)
に基いて増幅し、増幅した増幅信号を出力するセ
ンスアンプと、アース及び電源間に直列接続され
た第１、第２、第３、及び第４のＭＯＳ―ＦＥＴ
と、前記第２及び第３のＭＯＳ―ＦＥＴの接続点
に接続された共通バスと、前記増幅信号に基いて
、前記第１のＭＯＳ―ＦＥＴを駆動する第１の制
御信号、前記第１のＭＯＳ―ＦＥＴの駆動期間を
含む長い駆動期間で前記第２のＭＯＳ―ＦＥＴを
駆動する第２の制御信号、前記第４のＭＯＳ―Ｆ
ＥＴを駆動する第４の制御信号、及び前記第４の
ＭＯＳ―ＦＥＴの駆動期間を含む長い駆動期間で
前記第３のＭＯＳ―ＦＥＴを駆動する第３の制御
信号を出力する制御回路とを設けたことを特徴と
する信号出力回路。 (2) 前記センスアンプから出力される増幅信号
は一対の増幅信号であり、前記一対の増幅信号が
前記制御回路に入力することを特徴とする請求項
(1)記載の信号出力回路。 (3) 前記制御回路は複数の論理回路で構成され
ることを特徴とする請求項(1)記載の信号出力回
路。 (4) 前記制御回路は、前記一対の増幅信号の一
方の変化又は他方の変化に応じて前記第１及び第
４の制御信号を出力する第１の論理回路と、前記
一対の増幅信号の一方の変化に応じて前記第２の
制御信号を出力する第２の論理回路と、前記一対
の増幅信号の他方の変化に応じて前記第３の制御
信号を出力する第３の論理回路より構成されるこ
とを特徴とする請求項(2)記載の信号出力回路。[Claims for Utility Model Registration] (1) A sense amplifier that amplifies the potential difference generated between a pair of bit lines based on a drive signal and outputs the amplified signal, and a first amplifier connected in series between the ground and the power supply. , second, third, and fourth MOS-FETs
a common bus connected to a connection point of the second and third MOS-FETs; a first control signal for driving the first MOS-FET based on the amplified signal; a second control signal for driving the second MOS-FET in a long driving period including the driving period of the MOS-FET, and a second control signal for driving the fourth MOS-FET;
and a control circuit that outputs a fourth control signal for driving the ET and a third control signal for driving the third MOS-FET in a long driving period including the driving period for the fourth MOS-FET. A signal output circuit characterized by: (2) The amplified signal output from the sense amplifier is a pair of amplified signals, and the pair of amplified signals are input to the control circuit.
The signal output circuit described in (1). (3) The signal output circuit according to claim (1), wherein the control circuit is composed of a plurality of logic circuits. (4) The control circuit includes a first logic circuit that outputs the first and fourth control signals in response to a change in one of the pair of amplified signals or a change in the other, and one of the pair of amplified signals. and a third logic circuit that outputs the third control signal in response to a change in the other of the pair of amplified signals. The signal output circuit according to claim (2), characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP510988U JPH02838U (en) | 1988-01-19 | 1988-01-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP510988U JPH02838U (en) | 1988-01-19 | 1988-01-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02838U true JPH02838U (en) | 1990-01-05 |
Family
ID=31208195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP510988U Pending JPH02838U (en) | 1988-01-19 | 1988-01-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02838U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08235869A (en) * | 1994-12-19 | 1996-09-13 | Samsung Electron Co Ltd | Data input / output sensing circuit of semiconductor memory device |
-
1988
- 1988-01-19 JP JP510988U patent/JPH02838U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08235869A (en) * | 1994-12-19 | 1996-09-13 | Samsung Electron Co Ltd | Data input / output sensing circuit of semiconductor memory device |