JPH0397253A - Lead frame for integrated circuit - Google Patents

Lead frame for integrated circuit

Info

Publication number
JPH0397253A
JPH0397253A JP1235404A JP23540489A JPH0397253A JP H0397253 A JPH0397253 A JP H0397253A JP 1235404 A JP1235404 A JP 1235404A JP 23540489 A JP23540489 A JP 23540489A JP H0397253 A JPH0397253 A JP H0397253A
Authority
JP
Japan
Prior art keywords
chip
lead frame
die
junction
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1235404A
Other languages
Japanese (ja)
Inventor
Kenji Kubozono
久保薗　健治
Hisatoshi Ito
久敏 伊藤
Toshihiko Mori
俊彦 森
Toshihiro Kurita
栗田　敏広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1235404A priority Critical patent/JPH0397253A/en
Publication of JPH0397253A publication Critical patent/JPH0397253A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To fix an IC chip to lead frames without any junction by die bonding process by a method wherein the title lead frame is provided with a die pad part mounting the IC chip as well as a holder part holding the sides of the IC chip by spring tension at least in two directions. CONSTITUTION:It is recommended that a holder part 5 is formed in leaf spring type while the shape, dimension and thrusting pressure thereof avoid the slip and destruction of an IC chip in the later process. The IC chip 4 is mounted on a die pad part 1 while the four sides of the IC chip 4 are held by the spring tension of the holder part 5 and then lead parts 2 and the IC chip 4 are connected by connecting wires 6. During the processes, the junction by die-bonding process can be avoided thereby enabling the junction of IC chip 4 and the heating in the junction process causing thermal strain to be avoided. Furthermore, since the junction of the IC chip 4 and the lead frame parts 2 by die- bonding process is avoided, the die-bonding process can be eliminated from the package assembling process of integrated circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路（ＩＣ）に使用されるリードフレー
ム、特にダイボンディングによる接合を行うことな＜、
１Ｃチップをダイパッド部に固定できるリードフレーム
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to lead frames used in integrated circuits (ICs), particularly those that do not require bonding by die bonding.
The present invention relates to a lead frame capable of fixing a 1C chip to a die pad portion.

〔従来の技術〕[Conventional technology]

第５図は従来のリードフレームを示す斜視図である．図
において，（ｌ）はＩＣチップ（図示省略）を載せるた
めのダイバッド部、（２）はダイバッド部（１）の周辺
部に配置されたリード部であり．　ＩＣチップに接続ワ
イヤー等で接続されるようになっている．（３）はダイ
パッド部（１）を支持する支持部である． 上記のように構成された従来のリードフレームにおいて
は、集積回路の組立に際して、ＩＣチップをリードフレ
ームのダイパッド部（１）に接着層を介して接合してい
る。Figure 5 is a perspective view of a conventional lead frame. In the figure, (l) is a die pad portion on which an IC chip (not shown) is placed, and (2) is a lead portion placed around the die pad portion (1). It is connected to the IC chip using a connecting wire, etc. (3) is a support part that supports the die pad part (1). In the conventional lead frame configured as described above, when assembling an integrated circuit, the IC chip is bonded to the die pad portion (1) of the lead frame via an adhesive layer.

ところがダイボンディングによる接合では、ＩＣチップ
の素材となるＳｉとリードフレーム材の熱膨張係数の違
いにより、ダイボンド後に残留応力を生じ，チップのク
ラック発生や，内部応力の緩和による変形から、パッケ
ージ樹脂のクラック発生の誘因となることがある．この
ような現象は高集積化によるチップの大型化とともに顕
著になってきている． すなわち、ＩＣチップの素材Ｓｉの熱膨張係数は約３ｘ
ｌＯ−＠／’Ｃであり、一方リードフレーム材の素材に
は、鉄・ニッケル合金（４２Ａｌ１ｏｙ）あるいは銅合
金が使用されているが、前者の熱膨張係数は約６×１０
“／℃、後者は約１７　ｘ　１０−’　／　’Ｃであり
，この熱臓癲係数の差がＳｉチップのクラックあるいは
モールド樹脂のクラックの誘因となっている。However, in bonding by die bonding, residual stress is generated after die bonding due to the difference in thermal expansion coefficient between Si, which is the material of the IC chip, and the lead frame material, resulting in cracks in the chip and deformation due to relaxation of internal stress, resulting in damage to the package resin. This may cause cracks to form. This phenomenon has become more prominent as chips become larger due to higher integration. In other words, the thermal expansion coefficient of the material Si of the IC chip is approximately 3x.
lO-@/'C, and on the other hand, iron-nickel alloy (42Al1oy) or copper alloy is used as the lead frame material, and the thermal expansion coefficient of the former is approximately 6 x 10
The latter is approximately 17 x 10-'/'C, and this difference in heat evaporation coefficient is the cause of cracks in the Si chip or cracks in the molding resin.

４２Ａｌｌｏｙは銅合金に比べ、Ｓｉとの熱膨張差が小
さいため大きなチップに使用されているが、いずれにし
てもチップとリードフレーム材の熱膨張の差を緩和させ
る必要があった。42Alloy is used for large chips because it has a smaller difference in thermal expansion with Si than copper alloys, but in any case, it was necessary to alleviate the difference in thermal expansion between the chip and the lead frame material.

この熱膨張係数の差を緩和させる手段として，チップと
リードフレームを接合するダイボンド材の材質変更を行
い、例えばＡｕ−Ｓｉ共晶合金のＡｇぺ−ストのような
低温側で硬化する樹脂の採用により、より低温側でダイ
ボンディングを行うなど、熱膨張係数の差の改善がはか
られてきた。As a means to alleviate this difference in thermal expansion coefficient, we changed the material of the die bonding material that joins the chip and the lead frame, for example, we adopted a resin that hardens at low temperatures, such as Ag paste of Au-Si eutectic alloy. As a result, efforts have been made to improve the difference in thermal expansion coefficients, such as by performing die bonding at lower temperatures.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら，高集積化とともにチップサイズがさらに
大きくなり、一方では熱の発生も大きくなって、熱を放
散させる必要から，銅合金の必要性が高まるなど，従来
の改善では対応が困難なものへの対応が迫られてきてい
る．またこの熱膨張の差をできるだけ少なくするために
、ダイボンドされるリードフレーム材に十文字のスリッ
トを入れて応力を等価的に４分割してクラックを防止す
る方法も提案されているが、この場合、ＩＣチップを樹
脂層を介してリードフレーム材に接着する際、樹脂がス
リットより貫通してリードフレーム材の下方に到り，治
具と接合してしまい作業性が悪くなる等の問題点がある
。However, as chip size increases with higher integration, the generation of heat also increases, and the need for heat dissipation increases the need for copper alloys, which is difficult to deal with with conventional improvements. We are being forced to take action. In order to minimize this difference in thermal expansion, a method has also been proposed in which a cross-shaped slit is made in the lead frame material to be die-bonded to equivalently divide the stress into four parts to prevent cracks. When bonding an IC chip to a lead frame material through a resin layer, there are problems such as the resin penetrating through the slit and reaching the bottom of the lead frame material, bonding with the jig and impairing workability. .

本発明は上記のような問題点を解消するため、ＩＣチッ
プとリードフレームとをダイボンディングによる接合を
行うことな＜、１Ｃチップをリードフレームに固定でき
る集積回路用リードフレームを提供することを目的とす
る。In order to solve the above problems, it is an object of the present invention to provide a lead frame for an integrated circuit that can fix a 1C chip to a lead frame without joining the IC chip and the lead frame by die bonding. shall be.

〔課題を解決するための手段〕[Means to solve the problem]

この発明の集積回路用リードフレームは、集積回路に使
用されるリードフレームにおいて、ＩＣチップを載せる
ダイバッド部と、前記ＩＣチップの側面部を少なくとも
２方向からバネ圧により保持する保持部とを備えたもの
である． 〔作　用〕 本発明の集積回路用リードフレームにおいては、ＩＣチ
ップをリードフレームのダイバッド部に固定するために
，リードフレームのダイバッド部にリードフレームの一
部を利用した保持部を設け、そのバネ作用によりＩＣチ
ップをはめ込んで機械的にＩＣチップをリードフレーム
に固定する．この場合ＩＣチップとリードフレームとの
ダイボンディングによる接合を無くすことにより，熱歪
み発生の原因となるＩＣチップ接合および接合時の加熱
が無くなり，熱歪みの発生は無くなる。またＩＣチップ
とリードフレームとのダイボンデイングによる接合がな
いので、集積回路のパッケージの組立工程からダイボン
デイング工程を省略することができる．〔実施例〕 以下、本発明の一実施例を図について説明する．第１図
は実施例のリードフレームのダイバツド部を示す斜視図
、第２図はそのダイパッド部にＩＣチップを装着した状
態を示すＡ−Ａ断面図であり、図において、第５図と同
一符号は同一または相当部分を示す。ダイパッド部（１
）はバネ材からなり、その上に載せたＩＣチップ（４）
を４方向からバネ圧により保持するように、４辺から巻
返し片状の保持部（５）が伸びている．（６）はリード
部（２）とＩＣチップ（４）を接続する接続ワイヤであ
る。保持部（５）は板バネ状に形成されており、その形
状、寸法、押圧力はＩＣチップ（４）の寸法とリードフ
レームの形状に応じたものであれば良く、ＩＣチップ（
４）が後工程（モールド工程）で位置ずれせず、またＩ
Ｃチップ（４）を破壊しないものが好ましい。A lead frame for an integrated circuit according to the present invention is a lead frame used for an integrated circuit, and includes a die pad portion on which an IC chip is placed, and a holding portion that holds side portions of the IC chip from at least two directions with spring pressure. It is something. [Function] In the integrated circuit lead frame of the present invention, in order to fix an IC chip to the die pad portion of the lead frame, a holding portion using a part of the lead frame is provided in the die pad portion of the lead frame, and the holding portion is provided with a holding portion using a part of the lead frame, and the holding portion is provided with a holding portion using a part of the lead frame. The IC chip is inserted into the lead frame and mechanically fixed to the lead frame. In this case, by eliminating the bonding between the IC chip and the lead frame by die bonding, the IC chip bonding and the heating during bonding, which cause thermal distortion, are eliminated, and the occurrence of thermal distortion is eliminated. Furthermore, since the IC chip and the lead frame are not joined by die bonding, the die bonding process can be omitted from the integrated circuit package assembly process. [Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing the die pad portion of the lead frame of the embodiment, and FIG. 2 is a sectional view taken along line A-A showing the state in which an IC chip is attached to the die pad portion of the lead frame. indicate the same or equivalent part. Die pad part (1
) is made of spring material, and the IC chip (4) placed on top of it is made of spring material.
A holding part (5) in the form of a rolled-up piece extends from the four sides so as to hold it by spring pressure from four directions. (6) is a connection wire that connects the lead portion (2) and the IC chip (4). The holding part (5) is formed in the shape of a leaf spring, and its shape, dimensions, and pressing force may be in accordance with the dimensions of the IC chip (4) and the shape of the lead frame.
4) is not misaligned in the post-process (mold process), and I
It is preferable to use one that does not destroy the C chip (4).

上記のような構或の集積回路用リードフレームにおいて
は、ＩＣチップ（４）をダイバッド部（１）に載せ、そ
の４辺を保持部（５）によりバネ圧を利用して保持し，
リード部（２）とＩＣチップ（４）を接続ワイヤ（６）
で接続する．この場合、ダイボンデイングによる接合を
無くすことができ、熱歪み発生の原因となるＩＣチップ
（４）の接合および接合時の加熱が無くなり、熱歪みの
発生は無くなる．またＩＣチップ（４）とリードフレー
ム部（２）とのダイボンディングによる接合がないので
、集積回路のパッケージの組立工程からダイボンディン
グ工程を省略することができる。In the integrated circuit lead frame having the above structure, the IC chip (4) is placed on the die pad part (1), and its four sides are held by the holding part (5) using spring pressure.
Wire (6) connecting lead part (2) and IC chip (4)
Connect with . In this case, bonding by die bonding can be eliminated, and the bonding of the IC chip (4) and the heating during bonding, which causes thermal distortion, are eliminated, and the occurrence of thermal distortion is eliminated. Furthermore, since there is no die bonding connection between the IC chip (4) and the lead frame portion (2), the die bonding process can be omitted from the integrated circuit package assembly process.

第３図は他の実施例のダイバッド部を示す斜視図、第４
図はその装着状態を示すＢ−Ｂ断面図である。この実施
例では，保持部（５）はダイバツド部（１）に接続する
枠（７）から４方向に伸びており、前記実施例と同様に
ＩＣチップ（４）を保持する。FIG. 3 is a perspective view showing the die pad part of another embodiment;
The figure is a BB sectional view showing the attached state. In this embodiment, the holding part (5) extends in four directions from the frame (7) connected to the diverging part (1), and holds the IC chip (4) as in the previous embodiment.

試験例 実施例の集積回路用リードフレームを用い、ＩＣチップ
としてＳｉチップを保持したもの（実施例１〜４）、　
および従来のＡｇペーストを用い、ＳｉＩＣチップをダ
イボンデイングしたもの（比較例１〜４）について、Ｉ
Ｃの信頼性を試験した試験結果を表１に示す。Test Examples Using the integrated circuit lead frame of the example, holding a Si chip as an IC chip (Examples 1 to 4),
And for die bonding of SiIC chips using conventional Ag paste (Comparative Examples 1 to 4), I
Table 1 shows the results of testing the reliability of C.

表上における試験条件は次の通りである。The test conditions on the table are as follows.

試験個数：各条件２０個 耐湿性試験：６０℃で湿度９０％、１０００時間温度サ
イクル二一４０℃（３０分）〜１２５℃（３０分）をｌ
Ｏサイクル ヒートショック二〇℃（１５秒）〜１００℃（ｔＳ秒）
を５サイクル 振動試験：１ｋＨｚ、２０Ｇ、４分間 表１の結果より，耐湿性，振動試験では差が認められな
かったが、温度サイクル、ヒートショックでは、Ｓｉチ
ップとリードフレームとをダイボンディングにより接合
することな＜Ｓｉチップをリードフレームに固定するこ
とにより．　ＩＣの信頼性を高める効果が明らかである
。またこの効果の比較では、鉄・ニッケル合金より銅合
金の方が大きく、Ｓｉチップサイズが大きくなるに従っ
て顕著にあらわれる傾向にある。Number of test pieces: 20 for each condition Humidity test: 60°C, humidity 90%, 1000 hour temperature cycle 21 40°C (30 minutes) to 125°C (30 minutes)
O cycle heat shock 20℃ (15 seconds) to 100℃ (tS seconds)
5-cycle vibration test: 1kHz, 20G, 4 minutes From the results in Table 1, no difference was observed in the moisture resistance and vibration tests, but in the temperature cycle and heat shock, the Si chip and lead frame were bonded by die bonding. By fixing the Si chip to the lead frame. The effect of increasing IC reliability is clear. Further, in comparison of this effect, it is larger in copper alloy than in iron-nickel alloy, and tends to become more pronounced as the Si chip size increases.

すなわちＳｉとの熱膨張係数の差が大きい銅合金ほどダ
イボンド後の残留応力が生じ易く、また残留応力はＳＬ
チップサイズが大きくなるほど増加するため熱衝撃に脆
くなる。このため、ダイボンディングを行わない効果は
銅合金でＳＬチップサイズが大きくなるほど顕著になる
。In other words, the copper alloy with a larger difference in thermal expansion coefficient from Si is more likely to generate residual stress after die bonding, and the residual stress
This increases as the chip size increases, making it more susceptible to thermal shock. Therefore, the effect of not performing die bonding becomes more pronounced as the SL chip size increases with copper alloy.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、リードフレームに保持
部を形成することにより，ダイボンディングによるＩＣ
チップとリードフレームの接合を無くすことができ、こ
れにより、より信頼性の高い集積回路のパッケージが可
能となる．また、熱放散の点で銅合金のリードフレーム
を必要とする集積回路においてもその効果は大きく、有
用である．As described above, according to the present invention, by forming the holding portion on the lead frame, IC
It is possible to eliminate the bond between the chip and the lead frame, making it possible to package integrated circuits with higher reliability. It is also highly effective and useful for integrated circuits that require copper alloy lead frames in terms of heat dissipation.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は実施例のリードフレームのダイバッド部を示す
斜視図、第２図はそのダイパッド部にＩＣチップを装着
した状態を示すＡ−Ａ断面図、第３図は他の実施例のダ
イバッド部を示す斜視図、第４図はその装着状態を示す
Ｂ−Ｂ断面図，第５図は従来のリードフレームを示す斜
視図である。 各図中、同一符号は同一または相当部分を示し、（１）
はダイパッド部、　（２）はリード部，（４）はＩＣチ
ップ、（５）は保持部である。Fig. 1 is a perspective view showing the die pad part of the lead frame of the embodiment, Fig. 2 is a cross-sectional view taken along line A-A showing the state in which an IC chip is attached to the die pad part, and Fig. 3 is the die pad part of another embodiment. FIG. 4 is a sectional view taken along line B-B showing the mounted state, and FIG. 5 is a perspective view showing a conventional lead frame. In each figure, the same reference numerals indicate the same or corresponding parts, (1)
(2) is a lead portion, (4) is an IC chip, and (5) is a holding portion.

Claims (1)

【特許請求の範囲】[Claims] （１）集積回路に使用されるリードフレームにおいて、
１Ｃチップを載せるダイパッド部と、前記ＩＣチップの
側面部を少なくとも２方向からバネ圧により保持する保
持部とを備えたことを特徴とする集積回路用リードフレ
ーム。(1) In lead frames used for integrated circuits,
A lead frame for an integrated circuit, comprising: a die pad portion on which a 1C chip is placed; and a holding portion that holds side portions of the IC chip from at least two directions with spring pressure.
JP1235404A 1989-09-11 1989-09-11 Lead frame for integrated circuit Pending JPH0397253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1235404A JPH0397253A (en) 1989-09-11 1989-09-11 Lead frame for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1235404A JPH0397253A (en) 1989-09-11 1989-09-11 Lead frame for integrated circuit

Publications (1)

Publication Number Publication Date
JPH0397253A true JPH0397253A (en) 1991-04-23

Family

ID=16985593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1235404A Pending JPH0397253A (en) 1989-09-11 1989-09-11 Lead frame for integrated circuit

Country Status (1)

Country Link
JP (1) JPH0397253A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358905A (en) * 1993-04-02 1994-10-25 Texas Instruments Incorporated Semiconductor device having die pad locking to substantially reduce package cracking

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358905A (en) * 1993-04-02 1994-10-25 Texas Instruments Incorporated Semiconductor device having die pad locking to substantially reduce package cracking

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