JPH0398534U - - Google Patents
Info
- Publication number
- JPH0398534U JPH0398534U JP727590U JP727590U JPH0398534U JP H0398534 U JPH0398534 U JP H0398534U JP 727590 U JP727590 U JP 727590U JP 727590 U JP727590 U JP 727590U JP H0398534 U JPH0398534 U JP H0398534U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reference voltage
- digital signal
- voltage sources
- analog signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図ａ及び第２図ｂは第１図に示す回路のＤ
／Ａ変換を説明するための図、第３図は従来の技
術を説明するためのブロツク図、第４図ａ、第４
図ｂ、第４図ｃは第３図に示す回路のＤ／Ａ変換
を説明するための図である。図中１……入力デイ
ジタル信号、２……出力アナログ信号、３……Ｒ
−２Ｒ梯子形抵抗回路、４……増幅回路、５ａ…
…第１の加算回路、５ｂ……第２の加算回路、５
ｃ……第３の加算回路、６ａ……第１のスイツチ
、６ｂ……第２のスイツチ、６ｃ……第３のスイ
ツチ、６ｄ……第４のスイツチ、６ｅ……第５の
スイツチ、６ｆ……第６のスイツチ、７……デコ
ーダ、８……第１の基準電圧源、９……第２の基
準電圧源である。なお、図中同一符号は同一又は
相当部分を示す。
Figure 1 is a block diagram showing one embodiment of this invention, and Figures 2a and 2b are D of the circuit shown in Figure 1.
/A conversion; Figure 3 is a block diagram for explaining the conventional technology; Figures 4a and 4;
FIG. 4b and FIG. 4c are diagrams for explaining D/A conversion of the circuit shown in FIG. 3. In the figure 1...Input digital signal, 2...Output analog signal, 3...R
-2R ladder resistance circuit, 4...amplifier circuit, 5a...
...First addition circuit, 5b...Second addition circuit, 5
c...Third addition circuit, 6a...First switch, 6b...Second switch, 6c...Third switch, 6d...Fourth switch, 6e...Fifth switch, 6f ...Sixth switch, 7...Decoder, 8...First reference voltage source, 9...Second reference voltage source. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
に等しい段数を持つＲ−２Ｒ梯子型抵抗回路、上
記のＲ−２Ｒ梯子型抵抗回路の出力端に接続され
アナログ信号を出力する増幅回路、上記のＲ−２
Ｒ梯子型抵抗回路の各段に接続される加算回路、
複数の基準電圧源、上記の複数の基準電圧源と上
記の加算回路とを接続するスイツチ、外部から入
力されるデイジタル信号をデコードし上記のスイ
ツチの接続状態を制御するデコーダ、とを備えた
ことを特徴とする非線形Ｄ／Ａ変換回路。 An R-2R ladder resistor circuit having a number of stages equal to the number of bits of a digital signal input from the outside, an amplifier circuit connected to the output terminal of the R-2R ladder resistor circuit and outputting an analog signal, and an amplifier circuit that outputs an analog signal. 2
an adder circuit connected to each stage of the R-ladder type resistance circuit;
A plurality of reference voltage sources, a switch that connects the plurality of reference voltage sources and the addition circuit, and a decoder that decodes an externally input digital signal and controls the connection state of the switches. A nonlinear D/A conversion circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP727590U JPH0398534U (en) | 1990-01-29 | 1990-01-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP727590U JPH0398534U (en) | 1990-01-29 | 1990-01-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0398534U true JPH0398534U (en) | 1991-10-14 |
Family
ID=31510937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP727590U Pending JPH0398534U (en) | 1990-01-29 | 1990-01-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0398534U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5142415U (en) * | 1974-09-25 | 1976-03-29 |
-
1990
- 1990-01-29 JP JP727590U patent/JPH0398534U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5142415U (en) * | 1974-09-25 | 1976-03-29 |
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