JPH042193U - - Google Patents
Info
- Publication number
- JPH042193U JPH042193U JP4262390U JP4262390U JPH042193U JP H042193 U JPH042193 U JP H042193U JP 4262390 U JP4262390 U JP 4262390U JP 4262390 U JP4262390 U JP 4262390U JP H042193 U JPH042193 U JP H042193U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output terminal
- terminal
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Selective Calling Equipment (AREA)
Description
第１図はこの考案の一実施例によるテレメータ
装置を示す構成図、第２図は従来のテレメータ装
置を示す構成図、第３図はフレーム構成を示す説
明図、第４図は従来のテレメータ装置によるビツ
ト構成を示す説明図である。
図において１は複数のアナログ信号源、１ａは
第１のアナログ信号源、１ｂは第２のアナログ信
号源、１ｃは第Ｎのアナログ信号源、２はアナロ
グマルチプレクサ、３はアンプ、４はＡ／Ｄ変換
回路、５はセレクト回路、６はメモリ回路、７は
デジタル減算回路、８は差分データ、９は最大差
分データ回路、１０はデジタル加減算回路、１１
はシンクパターン発生回路、１２はフレームフオ
ーマツト回路、１３は回線データ出力である。な
お、図中、同一符号は同一、又は相当部分を示す
。
Fig. 1 is a block diagram showing a telemeter device according to an embodiment of this invention, Fig. 2 is a block diagram showing a conventional telemeter device, Fig. 3 is an explanatory diagram showing a frame structure, and Fig. 4 is a block diagram showing a conventional telemeter device. FIG. 2 is an explanatory diagram showing the bit configuration according to In the figure, 1 is a plurality of analog signal sources, 1a is a first analog signal source, 1b is a second analog signal source, 1c is an Nth analog signal source, 2 is an analog multiplexer, 3 is an amplifier, and 4 is an A/ D conversion circuit, 5 is a selection circuit, 6 is a memory circuit, 7 is a digital subtraction circuit, 8 is difference data, 9 is a maximum difference data circuit, 10 is a digital addition/subtraction circuit, 11
1 is a sync pattern generation circuit, 12 is a frame format circuit, and 13 is a line data output. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
信号源の出力を入力したアナログマルチプレクサ
と、このアナログマルチプレクサの出力端を入力
端に接続したアンプと、このアンプの出力端を入
力端に接続したＡ／Ｄ変換回路と、このＡ／Ｄ変
換回路の出力端に一方の入力端を接続したセレク
ト回路と、このセレクト回路の出力端に接続した
メモリ回路と、一方の入力端に上記メモリ回路の
出力端を接続し他方の入力端にはＡ／Ｄ変換回路
の出力端を接続しかつ出力端が上記セレクト回路
の制御端子に接続されたデジタル減算回路と、差
分データの最大値を発生する最大差分データ発生
回路と、一方の入力端に上記最大差分データ発生
回路の出力端を接続し他方の入力端に上記メモリ
回路の出力端を接続し、かつ制御端子が上記デジ
タル減算回路の出力端に接続されたデジタル加減
算回路と、シンクパターン発生するシンクパター
ン発生回路と、このシンクパターン発生回路の出
力端を入力端に接続し上記デジタル減算回路の出
力信号を入力したフレームフオーマツト回路とを
備えたことを特徴とするテレメータ装置。 A plurality of analog signal sources, an analog multiplexer to which the outputs of the plurality of analog signal sources are input, an amplifier to which the output end of the analog multiplexer is connected to the input end, and an A/D converter to which the output end of this amplifier is connected to the input end. A D conversion circuit, a select circuit with one input terminal connected to the output terminal of this A/D conversion circuit, a memory circuit connected to the output terminal of this select circuit, and one input terminal connected to the output terminal of the memory circuit. and a digital subtraction circuit whose other input terminal is connected to the output terminal of the A/D conversion circuit and whose output terminal is connected to the control terminal of the select circuit, and the maximum difference data that generates the maximum value of the difference data. a generation circuit, one input terminal is connected to the output terminal of the maximum difference data generation circuit, the other input terminal is connected to the output terminal of the memory circuit, and a control terminal is connected to the output terminal of the digital subtraction circuit. A sync pattern generating circuit that generates a sync pattern; and a frame format circuit that connects the output terminal of the sync pattern generating circuit to its input terminal and inputs the output signal of the digital subtractor circuit. Characteristic telemeter device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4262390U JPH042193U (en) | 1990-04-21 | 1990-04-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4262390U JPH042193U (en) | 1990-04-21 | 1990-04-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH042193U true JPH042193U (en) | 1992-01-09 |
Family
ID=31554328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4262390U Pending JPH042193U (en) | 1990-04-21 | 1990-04-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH042193U (en) |
-
1990
- 1990-04-21 JP JP4262390U patent/JPH042193U/ja active Pending
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