JPH04101253A - Operation testing system for ecc circuit of memory - Google Patents

Abstract

PURPOSE:To perform operation tests on the ECC circuit of a memory device without increasing the number of parts and without giving any electrical damage to the specimen by performing reading operation after making access to a ROM for testing and testing the error correcting operations of the ECC circuit by using dummy destruction data read-out from the ROM. CONSTITUTION:At the time of testing the operations of an ECC circuit, a ROM 3 for storing dummy destruction data is prepared and, after connecting the ROM 3 to a memory address bus 10, memory data bus 11, and a specific selected line 12 by means of a, for example, spring probe, reading operations are made by making access to the ROM 3. Then the dummy destruction data read out from the ROM 3 by the reading operations are inputted to the ECC circuit 4 so as to confirm that the dummy destruction data are modified. Therefore, the operations of the ECC circuit 4 can be tested without giving any electrical damage to the specimen 4 and without increasing the number of parts, such as a dummy data destruction circuit, etc., resulting in a contribution to an improvement in reliability.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for testing the operation of an ECC circuit in a memory device equipped with an ECC circuit, the present invention relates to a method for testing the operation of an ECC circuit in a memory device equipped with an ECC circuit, without causing electrical damage to a specimen.
For the purpose of testing the error correction operation of the ECC circuit, a test read-only memory (ROM) in which pseudo-destructive data is written is prepared, and the test read-only memory (ROM) is inserted into the memory of the above memory device. address bus,
Connect the memory data bus to a specific selection line, access the test read-only memory (ROM), perform a read operation, and use the read false image destruction data to detect errors in the ECC circuit of the memory device. Configure to test corrective action.

[Industrial application field]

The present invention relates to a method for testing the operation of an ECC circuit for correcting 1-bit data corruption in a memory device in a memory device equipped with an ECC circuit. ``With the recent demand for high reliability in computer systems, ECC circuits are used in memory devices to correct 1-bit data corruption in each word.

In devices that require high reliability, it is possible to virtually cause 1-bit data destruction without increasing the number of parts and without causing electrical damage to the memory device being tested. Therefore, it is required to be able to test whether the ECC circuit can normally correct the 1-bit data corruption.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram illustrating a conventional ECC circuit operation test method.

A conventional ECC circuit operation test is performed using the memory data bus 11 of a memory device (hereinafter sometimes simply referred to as a specimen).
For example, a pseudo data destruction circuit 5 that generates 1-bit data destruction is inserted into the read data bus of When it is analyzed and recognized as a read operation, the pseudo data destruction circuit 5 virtually destroys one bit of data, or in the case of a specimen that does not have the pseudo data destruction circuit 5, the ECC circuit By forcibly grounding any one bit of the memory data bus 11 between the memory data bus 1.4 and the memory 1.2, a one-bit error is generated, and the ECC circuit 4 It was confirmed via the system data bus 13 that the error had been corrected.

Therefore, in order to conduct an operation test of the ECC circuit 4 of the specimen, the pseudo data destruction circuit 5 must be provided in the specimen, or a part of the memory data bus 11 of the specimen must be forcibly destroyed. In devices that require high transferability, providing the pseudo data destruction circuit 5 increases the number of parts and reduces reliability, and also forces part of the memory data bus 11. In the method of destroying the specimen, there was a problem that it could cause electrical damage to the specimen, and there was a risk of lowering the reliability.

In view of the above conventional drawbacks, the present invention provides a memory device W (specimen) equipped with an ECC circuit without increasing the number of parts or with a minimum increase, or without causing electrical damage to the specimen. It is an object of the present invention to provide an operation test method for an ECC circuit that can confirm that the destructive data has been corrected by inputting pseudo-destructive data into the ECC circuit without having to modify the destructive data.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. The above-mentioned problems are solved by a memory ECC circuit operation test method configured as follows.

In a memory device equipped with an ECC circuit 4, a test read-only memory (ROM) in which pseudo-image destruction data is written is used.
) 3 is prepared, and the read-only memory (ROM) 3 for the test is connected to the memory address bus 10. Memory data bus 11. Connect to a specific selection line 12, access the test read-only memory (ROM) 3, perform a read operation, and use the read pseudo-destructive data to correct an error in the ECC circuit 4 of the memory device. Configure to test.

[Effect]

That is, according to the present invention, a test read-only memory (ROM) in which pseudo-destructive data is written in advance (hereinafter simply referred to as read-only memory (ROM)) is prepared, and the memory serving as a specimen is prepared. When testing a device, the read only memory (ROM) is connected to the test piece's memory address bus, memory data bus.

Then, by connecting to a specific selection line (enable line), the read-only memory (ROM) is accessed from a central processing unit (CPU) (not shown), a read operation is performed, and the read pseudo-destructive data is read. , by inputting it into the ECC circuit, correcting the 1-bit error existing in the pseudo-image destruction data, reading it out to the system bus, and comparing it with the expected value set in advance in memory etc. The E
The corrective operation of the CC circuit can be confirmed.

Therefore, in the present invention, it is possible to test the error correction operation of the ECC circuit without causing electrical damage to the specimen and without increasing the number of components such as a pseudo data destruction circuit in the specimen. This has the effect of greatly contributing to improving the reliability of the specimen.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing the principle configuration of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention, in which (a) shows a read-only memory storing pseudo-destructive data. (ROM
) shows an example of connection to the specimen, and (b) shows an example of a memory space in which pseudo-destruction data is stored.

In the present invention, a read-only memory (ROM) 3 storing pseudo-destructive data is prepared, and this read-only memory (ROM) 3 is connected to the memory address bus 10. Memory data bus 11. For example, a spring probe is connected to a specific selection line 12, the read-only memory (ROM) 3 is accessed to perform a read operation, and the pseudo-destructive data read in the read operation is sent to the EC.
A means for inputting the data into the C circuit 4 and confirming that the pseudo-image destruction data has been corrected is a necessary means for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, with reference to FIG. 1 and FIG. 2, an operation test method for an ECC circuit of a memory according to the present invention will be explained.

First, in the present invention, a read-only memory (ROM) 3 storing pseudo-image destruction data is prepared.

Then, as shown in FIG. 2(a), the read-only memory (ROM) 3 is connected to the memory address bus 10 of the specimen using, for example, a spring probe. Memory data bus 11. Connect to a specific selection line (enable line) 12.

As shown in Figure (b), the address space of the read-only memory (ROM) 3 is assumed to be, for example, a free area of the memory space of the test specimen, and the free space is The enable signal for access is
A specific selection line 1 of the decoder (DEC) 6 shown in FIG.
Configure it so that it is output to 2.

At this stage, the central processing unit (CPU, not shown)
When the read-only memory (ROM) 3 is accessed, the selection line 12 of the decoder (DEC) 6 is activated, and at that time, the read-only memory (ROM) 3 stored at the address set on the memory address bus 10 is activated. Pseudo-destructive data is read from the memory (ROM) 3 onto the memory data bus 11.

The read pseudo-destroyed data is input from the memory data bus 11 to the ECC circuit 4, the corrupted bits are corrected, and the data is output to the system data bus 13.

The central processing unit (CPU) checks the expected value stored in advance in the memory 1.2, etc., and calculates the E.
Check the corrective operation of the CC circuit 4.

If the decoder (DEC) 6 analyzes the system address and information on the control bus 14,
EM) 1. Or, if it recognizes that the access is to 121.2, the selection line 121. or 122 is energized, and
If the access is a write operation, the ECC circuit 4 adds a check bit to the data on the system bus 13,
The memory (MEM) 1. Or it can be written to 2.

The central processing unit (CPU) includes the memory (MEM) 1
．． Alternatively, by looking at the data written in the ECC circuit 2, the check pit generation operation of the ECC circuit 4 can be confirmed.

In this way, the check pit generation operation and error bit correction operation of the ECC circuit 4 can be confirmed.

In the above embodiment, the read-only memory (ROM)
3 was explained using an example in which the spring probe is connected to the specimen, but if the number of parts allows, the connection may be made through a connector. In addition, the memory of the specimen is
If it is originally a read-only memory (ROM) and there is an unused area, do not connect the independent read-only memory (ROM) 3 as described above and use the read-only memory (ROM) of the specimen. It goes without saying that the same effect can be obtained by writing pseudo-destructive data in an unused area in advance and reading it out.

As described above, in order to test the operation of an ECC circuit in a memory device equipped with an ECC circuit, the present invention prepares a read-only memory (ROM) 3 storing pseudo-destructive data; ROM) 3 to the memory address bus 10 of the test object (memory device). Memory data bus 11. For example, by connecting a spring probe to a specific selection line 12, the read-only memory (RO
M) 3 is accessed to perform a read operation, and the pseudo-destructive data read in the read operation is input to the ECC circuit 4 to confirm that the pseudo-destructive data has been corrected. be.

〔Effect of the invention〕

As explained in detail above, the ECC of the memory of the present invention
The circuit operation test method is to prepare a test read-only memory (ROM) in which pseudo-destructive data is written in a memory device equipped with an ECC circuit, and to insert the test read-only memory (ROM) into the memory device. Connect to the memory address bus, memory data bus, and specific selection lines of
The test read-only memory (ROM) is accessed to perform a read operation, and the read pseudo-destructive data is used to test the error correction operation of the ECC circuit of the memory device. The operation of the ECC circuit can be tested without causing electrical damage to the memory device under test, and without increasing the number of components such as a pseudo data destruction circuit in the test object. This has the effect of greatly contributing to improving the reliability of the specimen.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram explaining a conventional ECC circuit operation test method. It is. In the drawing, 1.2 is memory (MEM). 3 is read-only memory (ROM) for testing, or
Read-only memory (ROM). 4 is an ECC circuit, 5 is a pseudo data destruction circuit, and 6 is a decoder (DEC). 10 is a memory address bus. 11 is a memory data bus. 12, 120.121 is the selection line. 13 is a system data bus. 14 is a system address bus and a control bus. are shown respectively. Figure 2

Claims (1)

[Claims] In a memory device equipped with an ECC circuit (4), a test read-only memory (R
Prepare a read-only memory (ROM) (3) for the test and connect it to the memory address bus (10), memory data bus (11), and specific selection line (12) of the memory device. Connect the test read-only memory (ROM) (3), perform a read operation, and use the read pseudo-destructive data to test the error correction operation of the ECC circuit (4) of the memory device. An operation test method for an ECC circuit of a memory, characterized in that: