JPH04103192A - Connection verification device of printed wiring board - Google Patents

Abstract

PURPOSE:To enable the connection verification of a power supply layer and a ground layer divided by a partitioning line and a through-hole clearance to be mechanized by a method wherein a selection means which selects a through-hole related to the division of a copper foil region and a calculating means which calculates the shape of the copper foil region which is to be divided are provided to a region recognition section. CONSTITUTION:Concerning the through-hole clearance of a clearance memory 248, an outline overlap detection section 249 checks that the overlap of the outline vector of a copper foil region calculated by a region formation processing section 245 subsists or not, and when the outline overlap detection section 249 judges that the overlap is present, the overlap flag of the memory 248 is set. Only the through-hole clearance belonging to the same group with the through-hole clearance where the overlap flag is set is converted into a vector through a clearance data conversion section 2411, and the vector concerned is stored in a vector memory 242. By this setup, a process in which only through-hole clearances related to the division of the copper foil region calculated through partitioning lines are selected from numerous through-hole clearances is finished, and then the shape of the copper foil region which is to be divided is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a design CAD system for printed wiring boards, and more particularly to a connection verification device for printed wiring boards that verifies connections between power supply and ground layers.

[Prior Art] When designing a printed wiring board, it may be necessary to supply two or more series of different types of mold sources to the same layer.

For example, as shown in Figure 4(a), +5V and +12V
When supplying power to the same layer, it becomes necessary to design the component group 41 with the +5V series and the component group 42 with the +12V series in independent copper foil areas. Therefore, Figure 4 (
As shown in b), partition lines 43a, 4 are formed on the inner layer of the copper foil layer.
3b, 43c are provided, and these partition lines 43a, 43b,
Two series of component groups are arranged in the area surrounded by 43c, and it is verified whether the desired circuit power supply pins are connected to these component groups in the correct amount.

As such a connection verification device, for example, JP-A-43-
One disclosed in Japanese Patent No. 311575 is known.

The technology disclosed in this document inputs the partition line of the power supply layer or the earth layer from a digitizer, vectorizes the partition line, calculates the intersection of the vectors, and shapes the copper foil area with the calculated intersection as the apex. Recognize first. Next, the connection is verified by comparing the logical power information of the component pin connected to the copper foil area with the actually supplied power information.

However, the conventional connection verification apparatus has a drawback in that it cannot recognize when a copper foil area is divided by a through-hole clearance, as shown in FIG. 5, for example.

In other words, the copper foil region 51 constituting the power supply layer or the ass layer
If a through-hole clearance 52 that divides this copper foil region 51 into a part of the countless through-hole clearances existing within the copper foil region 51 exists between the partition lines 43b and 43c as shown in the figure, the copper foil region 51 A portion of the copper foil region 53 is separated by the through-hole clearance 52, and a separate copper foil region 53 is formed.

Conventional connection verification devices cannot recognize such divided copper foil regions 53, and there is a problem that defects are detected for the first time in the manufacturing inspection process of printed wiring boards8. This was done to solve the problem. Even if the copper foil area of the power layer or ground layer generated by the partition line is divided by the clearance, it can be detected correctly and the desired power or ground can be connected to the pin of the component. It is an object of the present invention to provide a printed wiring board connection verification device that can verify in advance a state in which the printed wiring board is not supplied.

[Means for Solving the Problems] The present invention provides a connection verification device for a printed wiring board that includes an area recognition unit that recognizes a copper foil area of a power layer or a ground layer of a printed wiring board. a sorting means for sorting out through-hole clearances that are involved in dividing the copper foil area from among the through-hole clearances existing in the power supply layer or the earth layer; A calculation means for calculating the shape is added.

[Operation] In the present invention, through-hole clearances that are involved in dividing the copper foil area are selected by a screening means newly provided in the area recognition section, and then the shape of the fRM area to be separated by the through-hole clearance is calculated. . Therefore, the area recognition unit can verify whether or not an appropriate power source or ground is supplied to the component pins present in this divided copper foil area.

[Example 2] FIG. 2 is a block diagram showing the configuration of a connection verification device 2 according to the present invention and input/output devices connected thereto. The pattern data of the power layer or the ground layer is input from the digitizer 1 to the connection verification device W2.

Further, the logical power supply and arrangement data of the components are stored in the memory 3, read from the memory 3, and input to the connection verification device 2. The output from connection verification device 2 is 1
It is output to the display device 5 and the printing device 6.

The pattern data of the power supply layer or the earth layer inputted from the digitizer 1 is sent to the pattern data storage section 22 via the input section 21 and is temporarily stored therein. Storage part 2
The pattern data stored in 2 can be displayed on the display device 5 via the display section 25.

The result is compared with the result recognized by the area recognition unit 24 which recognizes the copper foil area of the power supply layer or the ground layer from the pattern data stored in the logical power supply 2 of the component which is partially input from the memory 3.

The verification result from the comparison section 27 is output to the printing device 6 via the verification result output section 28. Note that the operation of the connection verification device 2, except for the area recognition section 24, is disclosed in detail in the aforementioned Japanese Patent Laid-Open No. 63-311575, so a description of this portion will be omitted.

Next, FIG. 1 shows an example of the area recognition section 24 that realizes the features of the present invention. FIG. 1 is a block diagram showing an example of the detailed configuration of the area recognition unit 24.
2, a data conversion unit 241 connected to 2, and a vector memory 242 that stores the converted partition line vector data.
, an intersection detection unit 243 that detects the intersection of vector data;
An overlap detection unit 244 that detects overlap of vectors, an area creation processing unit 245 that creates outline data of a copper foil area from vector data, and a vector buffer 246 that stores vector data of one copper foil area. A clearance memory 248 that retrieves and stores through-hole clearances from the pattern data storage unit 22, a contour detection unit 249 that detects the overlap between the outline of the copper foil area created by the area creation processing unit 245 and the through-hole clearance, and a through-hole clearance. A grouping processing unit 2410 that detects graphical overlap between the two, a clearance data conversion unit 2411 that converts the grouped through-hole clearances into vector data, and a shape in which the copper foil area created from the partition line is divided by the through-hole clearance. It consists of an area division recognition unit 2412 that recognizes the copper foil area, and an area storage unit 247 that stores the recognized copper foil area.

Steps for converting the pattern data of partition lines stored in the pattern data storage section 22 into vector data in the data conversion section 241, and partitioning the data with partition lines 61 to create copper foil area contours 62, as shown in FIG. is described in the above-mentioned Japanese Unexamined Patent Publication No. 63-311575, so its explanation will be omitted, but please refer to the flowchart shown in Fig. 3 for the procedure for calculating the shape of the copper foil area divided by the through-hole clearance. This will be explained in detail.

First, the through-hole clearance 59 of the power layer is inputted from the pattern data storage section 22, and the clearance memory 2
48 (step 301). Next, the contour detection section 249 checks whether or not the through-hole clearance in the clearance memory 248 overlaps with the contour vector 60 of the copper foil region calculated by the region creation processing section 245 (step 302).

FIG. 7 is a diagram illustrating an example of this implementation method. As shown in FIG. As shown in b), the radius 61 of the through-hole clearance 59 and the shortest ratio M62 from the center of the through-hole clearance to the contour vector 60 are compared, and the shortest distance 6 is determined.
2 is shorter than the radius 61, it is determined that there is an overlap, and the overlap flag 63 of the clearance memory 248 shown in FIG. 7(C) is set (step 303).

Next, the process moves to grouping processing (step 304) This grouping processing is performed by the grouping processing unit 24]0, and an outline of the processing is shown in FIG. 8. First, the group number 64 of the clearance memory 248 CP to the 8th
As shown in Figure (b) 1.2. ...Give a unique initial value of n, then find a combination where the center distance 65 of the through-hole clearance is smaller than the sum of the radii 61 as shown in Fig. 8(c), and select the combination with the larger group number 64. Update the value with the smaller value. By chaining this to all through-hole clearances,
Grouping ends.

Next, the process moves to through-hole clearance vectorization processing (step 306).

This vectorization process converts into clearance data only those through-hole clearances that belong to the same group as those for which the overlap flag 63 with the contour vector of the copper foil area is set, from among the through-hole clearances stored in the clearance memory 248. This is executed by converting it into a vector in the section 2411 and storing it in the vector memory 242 (steps 305 and 306).

FIG. 9A shows rules for vectorizing through-hole clearance 59, and represents converting one through-hole clearance 59 into a clockwise vector group. Further, FIG. 9B shows the result of vectorizing the through-hole clearances 59 belonging to the same group.

This completes the process of selecting those that are involved in dividing the copper foil area calculated from the partition line from among the countless through-hole clearances in the power supply layer or the ground layer.

Next, the process of calculating the shape of the copper foil area divided by the selected through-hole clearance will be explained.

First, the vector data of the through-hole clearance and the contour vector created by the 5-area creation processing section 245 are stored in the backing block memory 242, and the intersection of the two is detected by the intersection detection section 243.

Next, as shown in FIG. 1OA, the vectors are divided at the intersection, but if there are vectors that overlap in the same direction, only one vector is left and the others are deleted, as shown in FIG. 10B.

Vector data obtained as a result of the above division and overlap deletion processing is shown in FIG. 10C. This completes the intersection division and overlap deletion processing (step 309), takes out the obtained vector data to II and stores it in the vector buffer 246, creates area data from the data in the vector buffer 246, and uses the through-hole clearance to A region shape calculation process is performed by storing the shape of the divided copper foil region as region data in the region data storage unit 247 (step 308).

The detailed procedure will be explained below.

First, as shown in FIG. 11A, one arbitrary vector 71 is taken out from the vector memory 242 and moved to an empty vector buffer. Next, a vector whose starting point coincides with the ending point of the first vector 71 that was moved, and which is found first when searching clockwise around the ending point of the first vector, is stored in the vector memory. 242 to the vector buffer 24G.

In the case shown in the figure, 72 to 7 are candidates for the second vector.
4 are selected, and 73 of them are selected as the second vector. Similarly, a third vector is extracted from the second vector 73 and moved to the vector buffer 246.

In this way, the process is repeated in a chain, and if the end point of the vector just taken out from the vector memory 242 matches any of the start points of the vectors that have already been moved to the vector buffer 246, the point from the start point of the moved vector to the end point is determined. A closed figure whose outline is the series of vectors up to this point is stored in the area storage unit 247. If a vector having a connection relationship cannot be found before forming a closed figure, the vector buffer 246 is emptied, an arbitrary vector is taken out from the vector memory 242, and the process starts again from the procedure of moving it to the vector buffer 246.

Further, even when a closed figure can be formed and stored in the area storage section 247, the process returns to the series of processes for emptying the vector buffer 246 and extracting an arbitrary vector.

In this way, the process is repeated until the vector memory 242 becomes empty of vector data.
As shown in Figure B, the shape of the copper foil area divided by the through-hole clearance can be detected.

The following steps are the same as for conventional verification equipment.

Verify the connection between the power supply layer and the ground layer by comparing the logical power supply position information of the component pin and the calculated shape of the copper foil area.

[Effects of the Invention] As described above in detail based on the embodiments, in the present invention, the area recognition unit includes a sorting means for sorting out through-hole clearances that are involved in dividing the copper foil area, and Since a calculation means for calculating the shape of the copper foil area to be divided is provided, it is possible to mechanize the connection verification of not only the partition line but also the power supply layer and the earth layer divided by the through-hole clearance. Therefore, a significant effect can be expected in shortening the design time of printed wiring boards and reducing the occurrence of defects.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a detailed configuration of an area recognition unit of a connection verification device according to the present invention, and FIG. 2 is a block diagram showing a schematic configuration of a connection verification device for a printed wiring board to which the present invention is applied. Figure 3 is a flowchart explaining the procedure for calculating the shape of the copper foil area divided by through-hole clearance.
Chart 2: Figure 4 is an explanatory diagram illustrating the procedure for separating different power layer regions by partition lines, Figure 5 is an explanatory diagram illustrating how copper foil regions are separated by through-hole clearances, and Figure 6. is an explanatory diagram illustrating forming a copper foil area contour using a partition line, FIG. 7 is an explanatory diagram illustrating the process of detecting the overlap between a through-hole clearance and a contour vector, and FIG. 8 is an explanatory diagram illustrating a group of through-hole clearances. Explanatory diagram for explaining the conversion process, No. 9
Figures A and 9B are explanatory diagrams for explaining vectorization processing, Figures 10A, 10B, and 10C are explanatory diagrams for explaining intersection division and overlap deletion processing, and Figures 11A and 11B are diagrams for explaining vectorization processing. It is an explanatory diagram explaining shape calculation processing. In the figure, 1... Digitizer, 2... Connection verification device, 3... Part logical power supply and arrangement data storage memory, 22... Pattern data storage unit 24... ...Area recognition section, 27... Comparison section, 2
4 data converter, 242...vector memory,
243. - Intersection detection unit, 244. Overlap detection unit 24
5... Area creation processing unit, 246 Vector buffer, 247... Area storage unit, 248... Clearance memory, 249... Contour type detection unit, 2410...
. . . Grouping processing section, 2411 . . . Clearance data conversion section, 2412 . . . Area division recognition section. Patent applicant Oki Electric Industry Co., Ltd. Representative Patent attorney Takashi Kumagai (1 other person) 1 and 7 Riaushi also bθ゛ @ foil 4shi 1) Sheetζ !21 Figure 8 IC) 5 death through J gono V7 shi7ri〉λ
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Claims (1)

[Scope of Claims] An area recognition unit that recognizes copper foil areas of a power layer or a ground layer of a printed wiring board that are separated by a partition line pattern input from a digitizer and to which different power supplies are supplied. In the printed wiring board connection verification device, the area recognition section includes a sorting means for selecting through-hole clearances that are involved in dividing the copper foil area from among the through-hole clearances existing in the power supply layer or the earth layer; A connection verification device for a printed wiring board, comprising: calculation means for calculating the shape of a copper foil area divided by the selected through-hole clearance.