JPH0744585A - Design method of multilayer printed wiring board - Google Patents

Abstract

(57) [Summary] [Purpose] To prevent the generation of a power supply region that has lost electrical connection inside due to the chain of clearance lands in a multilayer printed wiring board. [Structure] When a clearance land 1 is generated, it is determined whether or not there is a clearance land 2 that is in contact with or intersects with the clearance land 1. If the clearance land 2 is present, it is contacted with the clearance land 2 or It is determined whether there is a clearance land 3 that intersects. Repeating this judgment, Clearance Land 1
A clearance land chain is generated by the clearance land 4. An alarm is issued to disable the occurrence of this clearance land chain, and the clearance land 4
Suppress the occurrence of.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a multilayer printed wiring board, and more particularly to a method for designing a multilayer printed wiring board having a power source and a ground layer as inner layers.

[0002]

2. Description of the Related Art As a conventional technique, for example, Japanese Patent Laid-Open No. 2-2
No. 47579 will be described with reference to FIGS.
FIG. 3 is a flow chart for explaining the design method of this conventional example, and FIG. 4 is a block diagram of the design apparatus. Figure 4
In this design device, the pattern data memory 1
2. Clearance data extraction unit 13, clearance data combination unit 14, closed loop creation unit 15, closed loop data memory 16, line segment removal unit 17, power supply point detection unit 18, dividing line extraction unit 19, pattern drawing 21 It is composed of an output unit 20 and a pattern data creation unit 22.

First, in step S11 of FIG. 3, the dividing line extraction unit 19 extracts the dividing line data from the pattern data memory 17 and creates the dividing line pattern 8. For example, in FIG.
In the case of the printed wiring board of (a), the power supply region of the inner layer of the substrate is divided into + 5V region and + 12V region by the dividing line 8.

Next, in step S12, the clearance land data extracting section 13 extracts the penetration point data of the inner layer from the pattern data memory 17, and divides it into the clearance land 1 and the exposure contact point (power supply point) 10. Next, in step S13, the clearance land joining unit 14 checks the overlap of the clearance lands, and if they overlap, joins their centers with a straight line. FIG. 5B shows a chain of straight line portions 9 in this case.

Next, in step S14, the closed loop generator 15
Traces the straight line portion 9 provided between the overlapping clearance lands and checks the intersection with the dividing line 8 to create closed loop data in which the closed loop 5 is detected. Hereinafter, this closed loop data will be referred to as floating island 5.

The floating island 5 and the remaining non-closed loop data are stored in the closed loop data memory 16. FIG. 5 (c)
Shows an example of the contents of the closed loop data memory. Next, the line segment removing unit 17 removes the line segment belonging to the non-closed loop in the closed loop data memory 16.

Next, in step S15, the power supply point detection unit 18 detects the power supply point 10 in the floating island 5, and the floating island 5 can be identified by its presence. In the case where the power supply point 10 is present in step S16, the process proceeds to step S17,
The drawing output unit 20 creates the pattern diagram 21 for the closed loop 5. At this time, the power supply point mark 10 is written on the floating island 5 including the power supply point 10 as shown in FIG.

On the other hand, when the power supply point 10 is not included in step S16, the process proceeds to step S18 and the floating island 5 is shown in FIG.
Hatching 11 is applied as shown in FIG.

[0009]

This conventional method for designing a multilayer printed wiring board has a problem that the floating islands 5 are formed at the stage of designing due to the overlapping of the clearance lands. Further, even after the inspection, the power supply region included in the floating island 5 does not have an electrical connection, and as a result, there is a problem that there is a portion to which power is not supplied. Since such floating islands 5 become an unstable factor in circuit operation, it is desirable that they do not occur during design.

An object of the present invention is to provide a method for designing a multilayer printed wiring board which solves such problems, eliminates the formation of floating islands, and enables stable pattern design.

[0011]

The structure of the method for designing a multilayer printed wiring board according to the present invention is such that a via hole for connecting each layer of the multilayer wiring board is opened and a land is formed at the intersection of this via and each layer. And a step of generating clearance lands corresponding to the lands in each of the inner layers, and when there is a clearance land in each of the inner layers, if there are clearance lands that the clearance lands contact or intersect, The method is characterized by including a step of determining a chain to determine whether or not a floating island is generated in each inner layer, and a step of invalidating the generation of the clearance land and generating an alarm when the floating island is generated.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart for explaining an embodiment of the present invention, and FIGS. 2 (a) to 2 (e) are schematic diagrams for explaining the present embodiment.

First, in step S1, the through vias 7 which are holes in the substrate used for connecting the wiring between the surface layers and the inner layers of the printed wiring board are opened, and the vias 7 are formed as shown in FIG. 2 (c).
A land (7) is automatically generated at the intersection of the inner layer and the inner layer. Next, in step S2, when the via 7 of the different net (wiring pattern of different potential) penetrates the solid 6 existing in the power / ground layer of the inner layer, in order to avoid the interference between the solid and the land, the clearance is provided between them. A clearance land 1 having a land shape of opening a hole is automatically generated.

Whether or not the clearance land 2 automatically generated in step S2 is in contact with or intersects in step S3 is determined by performing a graphic calculation. When the clearance land 2 exists in step S3, it is determined in step S4 by the graphic calculation whether or not the clearance land 3 that contacts or intersects with the clearance land 2 exists.

By repeating the steps up to step S4, the clearance land 4 is contacted as shown in FIG. 2 (a), or the clearance land 4 is judged to exist by intersecting the clearance land 4 and the clearance land 4 contacts the clear land 1. When crossing, it is judged that a chain of clearance lands exists. When it is determined in step S4 that there is a chain of clearance lands, it is determined in step S5 by graphic calculation whether the floating island 5 exists.

When it is determined in step S5 that the floating island 5 exists, the land 7 automatically generated in step S1.
And clearance land 1 automatically generated in step S2
Is invalidated and canceled in step S6, and immediately thereafter, an alarm is issued in step S7.

Next, as shown in FIG. 2B, a branch may exist in the middle of the chain of clearance lands. 1) When a through via 7 which is a hole in a substrate used for connecting wiring between surface layers and inner layers is opened, a land 7a is automatically generated at the intersection of this via 7 and the layer. 2) Clearance lands are automatically generated in the solid 6 existing in the power and ground layers of the inner layer. 3) Judgment is made by figure calculation as to whether or not there is a clearance land 2 which the clearance land automatically generated in 2) contacts and intersects. 4) When the clearance land 2 exists in 3), it is determined by graphic calculation whether or not the clearance land 3 contacting and intersecting the clearance land 2 exists.

When there is a branch from the clearance land 3 like the clearance land 31, the clearance lands other than the clearance land 3 are sequentially traced. First, the clearance land 32 has a chain, but the floating island 5 does not exist. Next, clearance land 3 which is a branch point
Returning to 1, the chain with the clearance land 33 is judged. These determinations are repeated, and it is determined that the clearance land 4 contacts and intersects with the clearance land 4. When the clearance land 4 contacts and intersects with the clearance land 1, it is determined that a clearance land chain exists. 5) If it is determined in 4) that a chain of clearance lands exists, it is determined by figure calculation in which the floating island 5 exists. 6) When it is judged that floating island 5 exists in 5), 1)
The land 7 and the clearance land 1 automatically generated in 2) are invalidated and canceled. 7) If it is invalid in 6), an alarm is issued immediately afterward and the process ends.

[0019]

As described above, according to the present invention, every time a land is generated in the method for designing a multilayer printed wiring board, a clearance land is generated in the ground layer of the inner power source corresponding to the land, and the clearance land is generated. By determining whether or not a floating island will occur in the inner layer depending on the land, and if the floating island occurs, by invalidating the generation of the land,
Floating islands are not formed during the design, and the power supply region is always electrically connected to the power supply, which has the effect of enabling stable design.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating the embodiment of FIG.

FIG. 3 is a flowchart for designing a conventional multilayer printed wiring board.

FIG. 4 is a block diagram showing the configuration of the designing device of FIG.

5 is a schematic plan view of a printed wiring board for explaining the operation of FIG.

[Explanation of symbols]

 1 to 4, 31 to 33 Clearance land 5 Floating island (closed loop, power supply area) 6 Solid of power supply or ground layer of inner layer 7 Through via (land) 8 Dividing line 9 Straight part 10 Exposure contact area (power supply area) 11 Hatching 12 pattern data memory 13 clearance data extraction unit 14 clearance data connection unit 15 closed loop creation unit 16 closed loop data memory 17 line segment removal unit 18 power supply point detection unit 19 split line extraction unit 20 drawing output unit 21 pattern diagram 22 pattern data creation unit

Claims (2)

[Claims] 1. A step of forming a via hole of a through hole connecting each layer of a multilayer wiring board to generate a land at an intersection of the via and the layer, and a clearance land corresponding to the land is formed in each of the inner layers. If there is a clearance land in each inner layer, and if there are clearance lands where the clearance lands contact or intersect with each other, the chain of these clearances is determined to determine whether or not a floating island occurs in each inner layer. A method for designing a multilayer printed wiring board, comprising: a step; and a step of invalidating the generation of the clearance land and generating an alarm when the floating island occurs. 2. The design of a multilayer printed wiring board according to claim 1, wherein when a branch exists in the chain of clearance lands, the clearance lands at the branch points are sequentially traced to determine the existence of floating islands from the chain. Method.