JPH0410465A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of performance as a device even when two semiconductor layers having different conductivity types are electrically connected through an arbitrary conductivity type impurity-doped polycrystalline semiconductor layer by interposing a metallic layer or a metallic silicide layer between the semiconductor layer having the conductivity type different from the polycrystalline semiconductor layer and the polycrystalline semiconductor layer. CONSTITUTION:No P-N junction is formed between the P-type region 9b of a polycrystalline silicon layer and an N-type polycrystalline silicon layer 7a by interposing a titanium silicide layer 21 between the P-type region 9b of the polycrystalline silicon layer and the N-type polycrystalline silicon layer 7a. Consequently, both a section between the P-type region 9b of the polycrystalline silicon layer and the titanium silicide layer 21 and a section between the titanium silicide layer 21 and the N-type polycrystalline silicon layer 7a can be formed in ohmic junctions. Accordingly, even when the P-type region 9b of the polycrystalline silicon layer and an N-type diffusion region 2 having mutually different conductivity types are electrically connected by using the N-type polycrystalline silicon layer 7a, the performance of a device is not deteriorated.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention has a multilayer structure including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. 1st. The present invention relates to a semiconductor device in which second semiconductor layers are electrically connected via an impurity-doped polycrystalline semiconductor layer interposed therebetween.

[Conventional technology]

FIG. 2 is an equivalent circuit diagram of a semiconductor memory element using complementary MO3) transistors. As shown in the figure, a flip-flop is constructed by cross-connecting two complementary inverters (2) and (2). The inverter (2) is constituted by a series connection of a PMOS transistor 11 and an NMO transistor 12 which share a gate with each other, the source of the PMOS transistor 11 is connected to a power supply 13, and the source of the NMOS transistor 12 is grounded. On the other hand, inverter I
' is a PMOS transistor 11 that shares the gate with each other.
' and NMO3) transistor 12' are connected in series, and the source of the PMOS transistor 11' is connected to the power supply 1.
3', and the source of the NMO3) transistor]2' is grounded.

and PMOS) - drain of transistor 11 and NM
O3) Node 15, which is the connection point with the drain of transistor 12, is PMO3I-transistor 11 of inverter
' and NMO3I- connected to the gate of transistor 12. On the other hand, the drain of PMOS transistor 11' and N
MO3) The node 15', which is the connection point with the drain of the transistor 12', is the PMOS transistor 1 of the inverter
1 and NMO5I - connected to the gate of transistor 12.

These nodes 15 and 15' serve as storage nodes that store mutually inverted information.

As an example of the semiconductor memory element shown in FIG.
88 (International Electro
There is a semiconductor device described in 198g). This semiconductor device has a multilayer structure including a plurality of impurity-doped polycrystalline silicon layers, and uses the plurality of impurity-doped polycrystalline silicon layers to perform MIS.
It forms an I-transistor structure.

FIG. 3 is a cross-sectional view showing the cross-sectional structure of such a semiconductor memory element described in I EDM88.

As shown in the figure, N is applied to the surface of single-crystal silicon substrate 1.
A type diffusion region 2 is selectively formed.

A polycrystalline silicon gate 4 is formed with a gate insulating film 3 formed between these N-type diffusion regions 2.2.

And, by these components 2 to 4, the N of the inverter
It constitutes the MOS transistor 12. In addition, in the figure, an N-type diffusion region 2' (only one of the two is shown in the drawing) is formed on a single crystal silicon substrate 1 which is insulated and isolated from a MOS transistor 12 via an isolation oxide film 5. ), the gate insulating film 3' and the polycrystalline silicon gate 4' constitute an NMOS transistor 12' of the inverter 2'. Note that the source-drain direction of the NMOS transistor 12' is perpendicular to that of the NMOS transistor 12.

Then, layers 1, 2, 4 excluding a part of the N-type diffusion region 2, a part of the isolation oxide film 5, and a part of the polycrystalline silicon gate 4'.
．． An insulating film 6 is formed on parts 4' and 5, and polycrystalline silicon is formed on a part of this insulating film 6, part of the N-type diffusion region 2, part of the polycrystalline silicon gate 4' and part of the isolation oxide film 5. A layer 7 (7a, 7b) is formed, and an insulating film 8 is formed on the layer 6.7b except for the portion where the polycrystalline silicon layer 7a is formed. A polycrystalline silicon layer 9 is selectively formed on the insulating film 8 and the polycrystalline silicon layer 7a. The region of polycrystalline silicon layer 9 corresponding to polycrystalline silicon layer 7b is N-type region 9a, and the other region 9b (
(including on polycrystalline silicon layer 7a) is a P small region. These constituent parts 7 to 9 constitute a PMO transistor 11 of an inverter I in which the polycrystalline silicon layer 7b is used as a gate and the P small region 9b of the polycrystalline silicon layer 9 is used as a drain and a source region. Note that the polycrystalline silicon layer 7a
are the drain of the PMOS transistor 11, the drain of the NMOS transistor 12, and the polycrystalline silicon gate 4.
', and is used for electrical connection with node 1 in Figure 2.
It corresponds to 5. Note that the PMOS transistor 11' of the inverter (2) is not shown.

In this way, a complementary inverter can be constructed using a multilayer structure consisting of polycrystalline silicon layers 7.9 electrically connected to each other.

[Problem to be solved by the invention]

By the way, since the electrical connection of the transistor is made by the polycrystalline silicon layer 7a, the polycrystalline silicon layer 7a needs to have a conductivity type of P type or N type. Here, if the polycrystalline silicon layer 7a is composed of N-type, the P small region 9b of the polycrystalline silicon layer 9 and the polycrystalline silicon layer
An N-junction is formed. On the other hand, the polycrystalline silicon layer 7a is
When configured with a type, the N-type diffusion region 2 and the polycrystalline silicon layer 7
A PN junction is formed between a and a.

In this way, when electrically connecting two semiconductor layers of different conductivity types using an impurity-doped polycrystalline semiconductor layer, the PN
Because of the junction, the direction in which current flows is restricted and the overall performance of the device is reduced.

This invention was made to solve the above problems, and even if two semiconductor layers of different conductivity types are electrically connected through an impurity-doped polycrystalline semiconductor layer of any conductivity type, The purpose is to obtain a semiconductor device whose performance does not deteriorate.

[Means to solve the problem]

The semiconductor device according to the present invention has a multilayer structure including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, and the semiconductor device has a multilayer structure including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The electrical connection with the semiconductor layer is made through the first or second layer interposed between them.
A metal layer is formed between the polycrystalline semiconductor layer and a semiconductor layer of a conductivity type different from the polycrystalline semiconductor layer among the first and second semiconductor layers. layer or metal silicide layer is interposed.

[Effect]

In this invention, a metal layer or a metal silicide layer is interposed between the polycrystalline semiconductor layer and the polycrystalline semiconductor layer among the first and second semiconductor layers of different conductivity types. Therefore, no PN junction is formed between this semiconductor layer and the polycrystalline semiconductor layer.

Especially the first one. When at least one of the second semiconductor layers is a polycrystalline semiconductor layer, effective interlayer connections can be realized in a semiconductor device in which an MIS transistor is formed using a plurality of impurity-doped polycrystalline semiconductor layers in a multilayer structure.

〔Example〕

FIG. 1 is a sectional view showing an embodiment in which a semiconductor device according to the present invention is applied to the semiconductor memory element shown in FIG.

As shown in the figure, a titanium silicide layer 2 is provided between the polycrystalline silicon layer 7a and the P-type head region 9b of the polycrystalline silicon layer 9.
1 is inserted.

Note that the other configurations are the same as those in FIG. 3, so explanations will be omitted.

A method for forming the semiconductor device shown in FIG. 1 will be described below. First, N-type diffusion regions 2, 2', gate insulating film 33', polycrystalline silicon gates 4, 4', isolation oxide film 5, insulating film 6, and polycrystalline silicon layer are formed on single crystal silicon substrate 1 by a known method. 7 (7a, 7b) and an insulating film 8 are formed. At this time, the insulating film 8 is formed on the entire surface. Further, the conductivity type of the polycrystalline silicon layer 7 is set to N type.

Then, the corresponding insulating film 8 on the polycrystalline silicon layer 7a is removed by photolithography to form an opening. Thereafter, a titanium (Ti) layer having a uniform thickness is formed over the entire surface by sputtering. Next, RTA (Rapid Tempera
The polycrystalline silicon layer 7 is formed by
A titanium silicide reaction occurs only in the titanium layer formed on top a, and the titanium layer is turned into silicide. Then, by removing only titanium using a chemical that does not melt titanium silicide but only melts pure titanium, a titanium silicide layer 21 is formed in a self-aligned manner as shown in FIG.

Then, after selectively forming a polycrystalline silicon layer 9 on the insulating film 8 and the titanium silicide layer 21, N-type and P-type impurities are selectively added to the polycrystalline silicon layer 9. As shown in the figure, an N-type region 9a and a P-type head region 9b are selectively formed in a polycrystalline silicon layer 9.

In this embodiment, the titanium silicide layer 21 is interposed between the P-type head region 9b of the polycrystalline silicon layer 9 and the N-type polycrystalline silicon layer 7a.
A PN layer is formed between the mold head region 9b and the N-type polycrystalline silicon layer 7a.
The structure is such that no bond is formed. Therefore, ohmic junctions can be formed between the P-type head region 9b of the polycrystalline silicon layer 9 and the titanium silicide layer 21 and between the titanium silicide layer 21 and the N-type polycrystalline silicon layer 7a. Therefore, even if the N-type polycrystalline silicon layer 7a is used for electrical connection between the P-type head region 9b of the polycrystalline silicon layer 9 of different conductivity types and the N-type diffusion region 2, the performance of the device does not deteriorate.

Note that when the conductivity type of the polycrystalline silicon layer 7a is set to P type, the titanium silicide layer 21 is interposed between the polycrystalline silicon layer 7a and the N type diffusion region 2. That is, the titanium silicide layer 21 is interposed between the P-type region 9a and the N-type diffusion region 2 of the polycrystalline silicon layer 9, which have a conductivity type different from that of the polycrystalline silicon layer 7a, and the polycrystalline silicon layer 7a. Bye.

Note that not only titanium silicide, but any metal or metal silicide can be used in place of the titanium silicide layer 21. However, it is preferable to use a high melting point metal such as titanium to avoid deterioration during the manufacturing process that involves high heat treatment. Further, if metal silicide is used, there is an advantage that it can be formed in a self-aligned manner as described above.

Further, the present invention is not limited to the above-mentioned example, but has a multilayer structure including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, and the first semiconductor layer and The electrical connection with the second semiconductor layer is established between the first or second semiconductor layer interposed therebetween.
It is applicable to all semiconductor devices formed through polycrystalline semiconductor layers of conductivity type.

〔Effect of the invention〕

As described above, according to the present invention, among the first and second semiconductor layers of different conductivity types, a metal layer is provided between the polycrystalline semiconductor layer and the semiconductor layer of a different conductivity type and the polycrystalline semiconductor layer. Or because a metal silicide layer is inserted,
No PN junction is formed between this semiconductor layer and the polycrystalline 4' conductor layer, and therefore, electrical connection between the two semiconductor layers of different conductivity types can be made through the impurity-doped polycrystalline semiconductor layer of any conductivity type. Even if this is done, the performance of the device will not deteriorate.

Especially the first one. When at least one of the second semiconductor layers □ is a polycrystalline semiconductor layer, effective interlayer connection is realized in a semiconductor device in which a MIS transistor is formed using a plurality of impurity-doped polycrystalline semiconductor layers in a multilayer structure. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a semiconductor memory element according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an equivalent circuit of a conventional semiconductor memory element, and FIG. 3 is a structure of a conventional semiconductor memory element. FIG. In the figure, 2 and 2' are N-type diffusion regions, 4°4' is a polycrystalline silicon gate, 7 (7a, 7b) are polycrystalline silicon layers, 9 (9a, 9b) are polycrystalline silicon layers, and 21 is a titanium silicon layer. It is a silicide layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) It has a multilayer structure including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, and the first semiconductor layer and the second semiconductor layer In a semiconductor device in which electrical connection is made through a polycrystalline semiconductor layer of a first or second conductivity type interposed therebetween, one of the first and second semiconductor layers is different from the polycrystalline semiconductor layer. A semiconductor device characterized in that a metal layer or a metal silicide layer is interposed between a conductive type semiconductor layer and the polycrystalline semiconductor layer.