JPH0410471A - High electron-mobility composite transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a high electron mobility composite transistor having ultra-high speed/large drive capability.

<Prior Art> ECL (emitter-coupled logic) is known as a basic circuit for high-speed electronic circuits using conventional bipolar transistors.

<Problem to be solved by the invention> However, ECL requires many transistors (4 to 5) to configure one logic gate, and also requires passive elements (resistance), so it is difficult to implement when integrated into an IC. The disadvantages are that it is difficult to control the resistance value and the power consumption is large. Moreover, as shown in FIG. 5, p n p / n
When connecting p n transistors in series, there was a problem in that they had to be connected through a diode for level shifting (in the case of Si, if this diode was not present, there was a point where both npn and pnp would be turned on). (This will destroy the transistor).

The present invention was made in order to solve the problems of the above-mentioned conventional technology, and aims at speeding up and improving drive capability by forming one inverter with one element using IV group compound semiconductors. The present invention aims to provide a high electron mobility composite transistor.

Means for Solving the Problems> The configuration of the present invention for solving the problems of the above-mentioned prior art is as follows:
-In a transistor using a group V compound semiconductor, l
It is characterized in that npn and pnp type elements are stacked and integrally formed, and a collector barrier is provided between the base and collector of each transistor.

Function> ■-By stacking npn and pnp type transistors using V-group compound semiconductors and providing a collector barrier between the base and collector of each l-transistor, one inverter is fabricated from one element. This results in faster speeds and lower power consumption.

<Example> FIG. 1 is a sectional view showing a laminated film structure showing an example of the present invention. In the figure, 1 is a semi-insulating substrate made of GaAs or InP, and 2 to 8 are A17GaAs, InGaAs, or InP that are epitaxially grown in alignment on the substrate 1.
It is an AlAs-based compound and is doped with n and p impurities. 2 is the first n layer, 3 is the second n layer,
4 is the first 9 layers, 5 is the third n layer, 6 is the fourth n layer, 7
is the second p-layer, 8 is the third p-layer, and these layers are M
Using a BE device, etc., layers are sequentially stacked to have a predetermined impurity concentration and thickness, and the necessary parts are exposed by one etching, and then electrically deposited! 9 to 14 are formed.

Figure 2 shows the band diagram of this composite transistor.From this band structure, the first n-layer in Figure 1 is the collector, the second n-layer is the collector barrier, the first p-layer is the base, and the third The n layer is the emitter and the first p layer (base)
The ultra-high speed npn) transistor is constructed so that only the hot electrons generated in the npn transistor are allowed to pass through.

In addition, by using the first nine layers as a collector, the third n-layer as a collector barrier, the fourth n-layer as a base, the second p-layer as a contact layer, and the third p-layer as an emitter, the fourth n-layer (
A pnp transistor is configured to allow only hot holes among holes generated at the base to pass through.

FIG. 3 shows the voltage/current characteristics of these transistors, and because they have a heterogap, they have a certain offset as shown in the figure.

This shows that unlike the transistor made of St, a level shift diode is not required.

FIG. 4 shows a state in which an inverter is constructed using the composite transistor of the present invention. Note that this inverter can be integrated as a five-terminal element by using electrodes 10, 12, and 13 in common.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, since +nPn and PnP type elements are stacked and formed, it can be manufactured with one inverter or one element. Since it is composed of only active elements, it is stably turned on in a complementary manner, and power consumption can be reduced.

In addition, since a collector barrier is provided between the base and collector of each transistor, only hot electrons and hot holes contribute to the operation, so the current flow is essentially ultra-high speed, resulting in ultra-high speed operation. can. Furthermore, since one bipolar transistor is always completely turned on, the driving capacity is large.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention. Fig. 2 shows the band structure of Fig. 1, Fig. 3 shows the current/voltage characteristics of a transistor with a heterogap, and Fig. 4 shows an inverter configured with the composite transistor of the present invention. FIG. 5 is a diagram showing a conventional inverter. 1... Substrate 12... First n layer, 3... Second n layer
layer.

Claims (1)

[Claims] A high electron mobility composite transistor using a III-V group compound semiconductor, characterized in that npn and pnp type elements are stacked and integrally formed, and a collector barrier is provided between the base and collector of each transistor. transistor.