JPH0410570A - solid state imaging device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a photoelectric conversion element and a solid-state imaging device using the same, and particularly to a photoelectric conversion element that non-destructively retains photoelectrically converted signal charges,
The present invention relates to a photoelectric conversion element capable of amplifying and converting a signal corresponding to this signal charge, and a solid-state imaging device using the same.

[Prior Art] In recent years, amplification-type photoelectric conversion elements that amplify and compress photoelectrically converted signal charges have been studied in solid-state imaging devices, etc., and one of them is a device that accumulates photocarriers in the base and emitters. There is a solid-state imaging device that uses a bipolar transistor type photoelectric conversion element (hereinafter referred to as a bipolar sensor) that outputs an output from the sensor.

FIG. 8 is a circuit configuration diagram of a photoelectric conversion section and a signal readout section of a solid-state imaging device using the above bipolar sensor.

In FIG. 8, 1 is a bipolar sensor, 2 is a capacitor for controlling the base potential of the bipolar sensor 1, and 3 is a capacitor for controlling the base potential of the bipolar sensor 1.
is a pMOS l-transistor for resetting the base potential of the bipolar sensor 1, and the bipolar sensor l and the 2° pMOS transistor 3 constitute one unit pixel. 4 is a vertical output line, 5 is a horizontal drive line, 6
7 is a MOS transistor for resetting the vertical output line 4; 7 is a capacitor for accumulating output signals from pixels; 8 is a MOS transistor for resetting the vertical output line 4;
is MO3I- for transferring the output from the pixel to the capacitor 7.
transistor, 9 is a horizontal output line, 10 is a MOS transistor for transferring the output of capacitor 7 to horizontal output line 9, 11
1 is a buffer MOS transistor selected by the vertical shift register to apply a driving pulse to the pixel;
2 is a preamplifier that outputs the sensor output; 13 is an input terminal for applying a pulse to the gate of the MOS transistor 6;
14 is an input terminal for applying a pulse to the gate of the MOS transistor 8, 15 is an input terminal for applying a drive pulse to the MOS transistor 11, and 16 is a pressure terminal.

FIG. 9 is a timing chart for explaining the operations of the photoelectric conversion section and the signal reading section.

As shown in FIG. 9, when the pulse φvc input to the input terminal 13 is maintained at a high level and the pulse output input to the input terminal 14 is set to a high level and the MOS transistor 8 is turned on, the vertical Since the output line 4 is fixed to GND through the MOS transistor 6, the capacitor 7 is also reset to GND.

Next, the pulse φvc is set to a low level, the MOS transistor 6 is turned off, and the horizontal drive line 5 and capacitor 7 are made floating. When the pulse φ8 input to the input terminal 15 is set to high level in this state, the base potential of the bipolar sensor 1 is raised through the capacitor 2, and a signal with a potential corresponding to the base potential of the base region where photocarriers are accumulated is generated. is output to the emitter.

Next, after setting pulse φA to low level, pulse φ8 to middle level, and pulse φVC to high level, pulse φ8
When set to low level, pMOS transistor 3 turns on.
state, and the base of the bipolar sensor 1 is grounded. When the level of the pulse φ8 goes from a low level to a high level, the base-emitter of the bipolar sensor 1 becomes in a forward bias state, and the base potential decreases due to the base current.

When the level of the pulse φ8 changes from a high level to a low level, the base potential decreases due to capacitive coupling through the capacitor 2, a reverse bias is created between the emitter and the base, and accumulation of optical carriers starts.

The solid-state imaging device described above has the advantage of being less susceptible to noise in the readout circuit system because it can amplify and read out the optical carriers accumulated in the base of the bipolar sensor that constitutes the pixel.

[Problems to be Solved by the Invention] However, in the conventional solid-state imaging device described above, when reading pixel signals, a forward bias is applied between the emitter and the base of the bipolar sensor, so that the photoelectric charge accumulated in the base is Some parts will always disappear. Since the amount of signal destruction fluctuates each time it is read, random noise becomes large. As described above, if the signal destruction is large, the signal becomes small and the noise becomes large, resulting in a problem of poor S/N ratio.

On the other hand, in order to suppress signal destruction, it is possible to increase the current amplification factor hri, but it is difficult to manufacture bipolar sensors for all pixels so that they have a uniformly large hFE, and variations in the pixel structure may be the cause. There is a problem in that fixed pattern noise becomes large.

The present invention provides a photoelectric conversion element and a solid-state imaging device that can solve the above problems.

[Means for Solving the Problems] The photoelectric conversion element of the present invention includes a first semiconductor region of one conductivity type, and a semiconductor region of the opposite conductivity type formed outside the first semiconductor region. a third semiconductor region formed inside the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; the second semiconductor region and the third semiconductor region; and a control electrode formed on the first semiconductor region between them with an insulating film interposed therebetween.

A solid-state imaging device of the present invention is characterized in that the photoelectric conversion element described above is used as a unit pixel.

[Function] The photoelectric conversion element of the present invention includes the first semiconductor region, the second semiconductor region and the third semiconductor region, and the first semiconductor region between the second semiconductor region and the third semiconductor region. A control electrode is formed on the semiconductor region via an insulating film to form an insulated gate transistor, and the photocharge is accumulated or the accumulated photocharge is transferred to the floating first semiconductor region. , ■ of the insulated gate transistor due to potential changes in the first semiconductor region. By reading the signal using the fluctuation as a change in the output, a signal corresponding to the accumulated charge is output completely non-destructively during reading.

The solid-state imaging device of the present invention uses the photoelectric conversion element described above as a unit pixel, and outputs a signal corresponding to the charge accumulated in each pixel.

[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

Note that the photoelectric conversion element of the present invention is not limited to solid-state imaging devices (it can also be used for other purposes).

FIG. 1 is a plan view of one pixel of the photoelectric conversion section of the first embodiment of the solid-state imaging device of the present invention, and FIG.
3 is a longitudinal sectional view taken along Y-Y' of FIG. 1.

In FIGS. 1, 2, and 3, 17 is an n-region with a low impurity concentration, 18 is a silicon oxide film, and 19 is a P-type well in which photocharges are accumulated. There is. 20 is an n''' region which serves as an element isolation region in the Y-Y' direction and a drain of a MOS transistor, and 21 is an M
OS) n''' area which becomes the source of the transistor, 22 is M
Horizontal drive line 2, which serves as the gate of the OS transistor and also serves as the gate of the P-type MO8I-transistor, which uses the P-type well adjacent in the x-x' direction as the source and drain.
3 is a vertical output line connected to the n' region 21 which becomes the source;
Reference numeral 24 indicates a contact hole for connecting the n' region 21 serving as a source and the output line 23, and 25 indicates an interlayer insulating film.

FIG. 4 is an equivalent circuit diagram of the photoelectric conversion section and signal readout section of the first embodiment of the solid-state imaging device of the present invention.

Note that constituent members common to those in FIG. 8 are designated by the same reference numerals, and explanations thereof will be omitted.

In the figure, 26 is a MOS transistor having a capacitor (P well) that constitutes a pixel, and 27 is a reset M
28 is a MOS transistor for resistive load; 29 is an input terminal for applying a pulse to the gate of the MOS transistor 28;

FIG. 5 shows drive pulses for operating the sensor pixels in FIG. 4.

The timing chart in FIG. 5 is the same as that shown in FIG. 9 except for the pulse φ7, but when reading signals from the pixel, the pulse φ9 input to the input terminal 29 becomes high level, and the MOS transistor 28 and MOS transistor 26 form a source follower.

The high level value of the pulse φ8 input to the input terminal 15 is set to a level sufficient to turn on the MOS transistor 26, and the voltage applied to the power supply terminal 27 is a negative voltage, The P-well potential is set to be negative even when the P-well is reset, and the reverse bias between the source and the P-well is maintained even during pixel reading.

When the signal readout operation as described above is performed, the charge in the P well is completely non-destructive when the pixel is output, so there is no decrease in signal due to charge destruction or increase in random noise as in the conventional example, and a high S/ A solid-state imaging device with a high N ratio can be provided.

FIG. 6 is an equivalent circuit diagram showing one pixel and a unit readout system of a photoelectric conversion section showing a second embodiment of the solid-state imaging device of the present invention.

Capacity 7 in Figure 4. MOS transistor 8, horizontal output line 9. MOS transistor 10. In this embodiment, two circuits for signal accumulation and horizontal transfer, each consisting of the input terminal 14, are provided in parallel, and the capacitors 7-1. MOS transistor 8-1. Horizontal output line 9-1. MOS) transistor 1
0-1. Input terminal 14-1, and capacitor 7-2. MOS transistor 8-2. Horizontal output line 9-2. MOSl-transistor 10-2. A circuit is formed by the input terminal 14-2.

The pixel section also includes the n-type MOS transistor 26 already explained in FIG. It consists of a transistor 30. This p-type MO3) transistor 30 is formed so that when charge is transferred, the source of the photoaccumulation part is completely depleted and the number of holes becomes O.

The signal readout operation of such a solid-state imaging device is performed as follows.

First, the pulse φ賎 input to the horizontal drive line 5 is set to high level, and the pulse φVC is set to high level to MO
The S transistor 6 is turned on and the P well of the MOS transistor 26 is reset. Immediately after this, the reset output is accumulated in the capacitor 7-1 through the MOS transistor 8-1 by the source follower of the MOS transistor 26 and the MOS transistor 28.

Next, the pulse φ8 input to the horizontal drive line 5 is set to low level, and the photocharge is transferred from the source of the MOS transistor 3o to M
After transferring to the P-well of the OS transistor 26, the MOS
A signal output is accumulated in the capacitor 7-2 through the MOS transistor 8-2 by the source follower of the transistor 26 and the MOS transistor 28.

Each with a capacity of 7-1. The output of capacitor 7-2 is horizontal output line 9
-1.9-2, and by subtracting both signals, a final sensor output from which noise components have been removed can be obtained.

When the pixel section is in a dark state, the number of holes transferred to the P well of the MOS transistor 26 is zero.

In addition, since the charge in the P-well is not destroyed during readout, the output accumulated in capacitors 7-1 and 7-2 is the same in the dark state, and the fluctuation of the P-well charge when resetting the P-well Random noise caused by this and fixed pattern noise caused by non-uniformity during pixel formation are not included in the final sensor output obtained by taking the difference, making it possible to provide a solid-state imaging device with an extremely high S/N ratio.

FIG. 7 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied.

In the figure, an image sensor 201 in which optical sensors are arranged in an area is subjected to television scanning by a vertical scanning section 202 and a horizontal scanning section 203.

The signal output from the horizontal scanning section 203 is sent to the processing circuit 20.
4 and output as a standard television signal.

Drive pulse φ for vertical and horizontal scanning units 202 and 203
Mm, φMl+ φHN + φVl++ φshi1. φv2 etc. are supplied by the driver 205. The driver 205 is also limited by the controller 206.

[Effects of the Invention] As explained above, the photoelectric conversion element of the present invention accumulates photocharges in the first semiconductor region or transfers the accumulated photocharges, and converts the photoelectric conversion element into an insulated gate transistor by the back gate bias effect. By reading out the output changes due to fluctuations in Vl, it is possible to output a signal corresponding to the accumulated charges without destroying the accumulated charges at the time of reading.

Furthermore, since the second semiconductor region is outside the first semiconductor region and has the same potential as the substrate, there is no need for wiring for supplying voltage to the second semiconductor region.

In addition, in a conventional bipolar sensor in a solid-state imaging device, a readout pulse must be applied for the same time to all pixels, and in order to shorten the RC time constant of the horizontal drive line, the drive line is lined with aluminum. However, in the present invention, there is no such need and pixels with a high aperture ratio can be formed.As a result, it is possible to provide a solid-state imaging device with a high SZN ratio. I can do it.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of one pixel of a photoelectric conversion section of a first embodiment of a solid-state imaging device of the present invention. FIG. 2 is a longitudinal sectional view along line xx' of FIG. FIG. 3 is a vertical sectional view taken along the line YY' in FIG. 1. FIG. 4 is an equivalent circuit diagram of the photoelectric conversion section and signal readout section of the first embodiment of the solid-state imaging device of the present invention. FIG. 5 is a timing chart for explaining the operations of the photoelectric conversion section and signal readout section of the first embodiment. FIG. 6 is an equivalent circuit diagram showing one pixel and a unit readout system of a photoelectric conversion section showing a second embodiment of the solid-state imaging device of the present invention. FIG. 7 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied. FIG. 8 is a circuit diagram of a photoelectric conversion section and a signal output section of a solid-state imaging device using the bipolar sensor. FIG. 9 is a timing chart for explaining the operations of the photoelectric conversion section and the signal succession section. 1 is a bipolar sensor, 2 is a capacitor, 3 is a pMOS transistor, 4 is a vertical output line, 5 is a horizontal drive line, 6 is a MOS transistor for reset, 7 is a capacitor, 8 is a MOS transistor for transfer, 9 is a MOS transistor for transfer. Horizontal output line, 10 is a transfer MOS transistor, 11 is a buffer MOS transistor, 12 is a preamplifier, 13 is an input terminal, 14 is an input terminal, 15 is an input terminal, 16 is an output terminal, 17 is n
- region (base), 18 is a silicon oxide film, 19 is a P-type well, 20 is an n'' region, 21 is an n0 region, 22 is a horizontal drive line, 23 is a vertical output line, 24 is a contact hole,
25 is an interlayer insulating film, 26 is an MO having a capacitor (well)
S transistor, 27 is a power supply terminal, 28 is a MOS transistor for resistive load, resistor, 2 is a MOS output line, 14-29 is an input terminal, 30 is a pMOS transistor, 7-1.7-2 is a capacitor, 8 -1.8- Transistor 9-1.9-2 is horizontal 0-1.10-2 is MOS) Rungis 1.14-2 is an input terminal. Figure 1

Claims (2)

[Claims] (1) a first semiconductor region of one conductivity type; a second semiconductor region of a conductivity type opposite to that of the first semiconductor region formed outside the first semiconductor region; and the first semiconductor region. a third semiconductor region of a conductivity type opposite to that of the first semiconductor region formed inside the semiconductor region; and an insulating film on the first semiconductor region between the second semiconductor region and the third semiconductor region. A photoelectric conversion element comprising: a control electrode formed through the control electrode; (2) A solid-state imaging device using the photoelectric conversion element according to claim 1 as a unit pixel.