JPH04106789A - Memory cell circuit for sram - Google Patents

Abstract

PURPOSE:To stably hold the written data by providing an impedance control means for controlling the impedance of a load means for constituting a latch circuit in response to an operation mode of a memory cell circuit. CONSTITUTION:In the case a memory cell is in an access state, a level of a control voltage Vc becomes the highest value VH in a write operation. According ly, a current I6 having a value IH flows through a transitor TR 6a and 6b. In a read-out operation of the memory cell, the voltage having the lowest value VL is applied, therefore, the current I6 having a value IL flows through the TR 6a and 6b. Also, in the case the memory cell is in a non-selection state, the control voltage Vc having a middle value VM is applied, and the current I6 having a value IM flows. As a result, in the write operation, write of a data signal can be executed easily, and on the other hand, in the read operation, it can be realized that the stored data signal is not broken down by charge of a pair of bit lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention generally relates to memory cell circuits for SRAM,
In particular, SRAM can stably hold written data.
The present invention relates to a memory cell circuit for use in a computer.

[Prior Art] FIG. 6 is a circuit diagram of a conventional NMO3 type memory cell. The second memory cell circuit basically consists of a latch circuit using cross-coupled inverters and an access gate.

Referring to FIG. 6, la and lb are bit lines, 2 is a word line, 3a, 3b, 4a and 4b are NMOS transistors, 7 is a ground potential, 8 is a power supply potential, 10a and 10b are storage nodes, 15a 15b is a load element. In FIG. 6, NMOS transistors 4a, 4b and load elements 15a, 15b constitute two inverters, and their cross-coupling constitutes a latch circuit.

When data is written, storage nodes 10a and 10
Among b, one has a high potential and the other has a low potential. Since the transistor 4a or 4b whose gate is connected to the high potential storage node is turned on, a current flows from the power supply potential to the ground potential via the load element. Load element 15a
, 15b, the enhancement type N shown in FIG. 7A.
A MOS transistor or a depletion type NMOS transistor shown in FIG. 7B is used, but a large capacity SR
In the AM memory cell, a high resistance shown in FIG. 7C is used as a load element. High resistance load type memory cells are
It has become the mainstream of NMOS memory cells.

High resistance load type memory cells are LOGΩ to 100GΩ
By using high-resistance polysilicon, the resistance value will be from MΩ to ITΩ.

Therefore, 10-' per memory cell. or 1
A low memory cell current of 0-''A can be obtained, and the occupied area can be reduced.

Therefore, it can be said that it is suitable for reducing power consumption and increasing integration.

FIG. 8 is a circuit diagram of a conventional CMO3 type memory cell. In FIG. 8, la and lb are bit lines, 2 is a word line, 3a, 3b, 4a, 4b are NMOS transistors, 7 is a ground potential, 8 is a power supply potential, 16a, 16b
is a PMOSI-transistor. cb shown in Figure 8
ios type memory cell circuit MOS transistor 1
Since 6a and 16b are used as load elements, there is no direct current bus flowing from the power supply to ground during the data retention period. Very small leakage currents (≦10
-"A)L is not consumed. Therefore, the standby current of this memory cell circuit is about several nA.

On the other hand, gate array type integrated circuits are generally not equipped with special load circuits such as high-resistance polysilicon to reduce the current consumption of memory cells. Therefore, the high resistance load type memory cell circuit shown in FIG. 6 is not used, but the CMO5 type memory cell circuit shown in FIG. 8 is used.

[Problems to be Solved by the Invention] In the conventional SRAM memory cell circuit, the data signals left on the bit line pair 1a and lb in the immediately previous read cycle cause the data signals that remain on the bit line pair 1a and lb to cause other memories connected to the same bit line pair to This may occur if the data signal is erroneously written to the cell. That is, when the access gate transistor in another memory cell is turned on in response to the potential of the word line, the data signal remaining on the bit line pair is written. In conventional memory cell circuits, in order to prevent this problem, the current driving ability of the transistors 3a and 3b forming the access gate is smaller than the current driving ability of the transistors 4a and 4b forming the latch circuit shown in FIG. It was set. However, transistor 3a
, 3b is set too small than that of transistors 4a and 4b, a write operation becomes impossible. Therefore, it has been difficult to achieve both stable retention of data stored in memory cells and ease of writing operations to the memory cells.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to stably hold written data in an SRAM memory cell circuit.

[Means for Solving the Problems] An SRAM memory cell circuit according to the present invention includes a latch circuit connected to a bit line via an access gate means. The latch circuit includes first
and second inverter means. The first inverter means includes a first load means and a first switching means connected in series between the first and second power supply potentials. The second inverter means includes a second load means and a second switching means connected in series between the first and second power supply potentials. The memory cell circuit further includes impedance control means for controlling impedances of the first and second load means in response to an operating mode of the memory cell circuit.

[Function] In the SRAM memory cell circuit according to the present invention, the impedance control means controls the impedance of the first and second load means in response to the operation mode of the memory cell circuit. Therefore, since the impedance can be controlled to a predetermined value only in a desired operating mode, erroneous data writing can be prevented.

[Embodiment of the Invention] FIG. 1 is a circuit diagram of an SRAM memory cell circuit showing an embodiment of the invention. With reference to Figure 1, la, l
b is a bit line, 2 is a word line, 3a, 3b, 4a and 4b are NMOS transistors, 5a and 5b are PMOS transistors, and 6a.

6b is an npn bipolar transistor, 7 is a ground potential,
8 is a power supply potential, 9 is a control terminal, and 10a and 10 are storage nodes.

Transistors 6a and 4a are connected in series between power supply potential 8 and ground potential 7. Similarly, transistor 6
b and 4b are also connected in series between power supply potential 8 and ground potential 7. Transistors 6a and 4a constitute an inverter, and transistors 6b and 4b constitute an inverter. These two inverters are cross-coupled to form a latch circuit. The base of transistor 6a is connected to power supply potential 8 via transistor 5a. The base of transistor 6b is also connected to power supply potential 8 via transistor 5b. The gates of transistors 5a and 5b are connected to control terminal 9 to receive impedance control signal Sc.

FIG. 2 is a characteristic diagram of impedance control transistors 5a and 5b shown in FIG. 1.

This figure shows the dependence of the drain-source voltage a I d s on the gate-source voltage Vgs when the drain-source voltage Vds of the PMOS transistors 5a and 5b is constant. In the range lVgsl<Vth (vth is the threshold voltage), the Ids of the transistor is lVgsl
It changes in proportion to the index of Therefore, it is possible to greatly change the current 1ds with a small change in the voltage Vgs.

When Vgs-OV, the value 1Ids1 is 1pA to 10
When it becomes 0 pA and lVgsl=Vth, l Ids
l is several mA. When this current is amplified using transistors 6a and 6b shown in FIG.
Current amplification factor h of bipolar transistors 6a and 6b
Assuming +-8 is 100, approximately 100 pA to 10
A variable current source of 0 mA will be configured.

FIG. 3A is a voltage level diagram of the control voltage applied to terminal 9 shown in FIG. 1. Further, FIG. 3B is a current level diagram of the current ff116 flowing through the bipolar transistors 6a and 6b shown in FIG. 1. When the memory cell is in the access state, the level of control voltage Vc becomes the highest value V in the write operation. Therefore, a current I6 with the highest value 8 flows through transistors 6a and 6b. In the read operation of the memory cell, since the control voltage Vc having the lowest value V is applied, a current i16 having the lowest value IL flows through transistors 6a and 6b. Furthermore, when the memory cell is in a non-selected state, a control voltage Vc having an intermediate value V is applied, and an intermediate value 1. A current I6 with
flows.

As a result, in a write operation, a data signal can be written easily, while in a read operation, a stored data signal can be prevented from being destroyed by charges on the bit line pair. Further, in the non-selected state, the value of the current I6 can be lowered (IM) within a range where the stored data signal is not lost, so that the current consumption in the standby state can be reduced. That is, by controlling the control voltage VC according to the operation mode of the memory cell, it is possible to control the impedance of the load elements of the two inverters that constitute the latch circuit, and as a result, the above advantages can be obtained. become.

In the embodiment shown in FIG. 1, the PMOS transistor 5a
, 5b and the npn transistors 6a and 6b, the present invention is not limited to this embodiment.
For example, the present invention can also be applied to a circuit shown in FIG. 4 which is complementary to that shown in FIG.

FIG. 5 is a block diagram of a B1CMOS gate array to which the memory cell circuit shown in FIG. 1 or 4 can be applied. Referring to FIG. 5, 20 is a human output buffer area, 21 is an internal gate area, 22 is an SRAM area, and 23 is a control circuit. The memory cell circuit shown in FIG. 1 or 4 can be configured within the SRAM eA area 22. The control circuit 23 generates a control voltage Vc for impedance control and supplies it to the memory cell circuit in the SRAM area 22. In this way, the present invention
It is pointed out that it is applicable to B1C0M5 gate arrays with AM regions.

[Effects of the Invention] As described above, according to the present invention, the impedance control means for controlling the impedance of the load means constituting the latch circuit in response to the operation mode of the memory cell circuit is provided. An SRAM memory cell circuit capable of stably holding data was obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an SRAM memory cell circuit showing an embodiment of the present invention. FIG. 2 is a characteristic diagram of the impedance control transistor shown in FIG. 1. 3rd A
The figure is a voltage level diagram of the impedance control voltage applied to the terminal 9 shown in FIG. 1. FIG. 3B is a current level diagram of the current flowing through the bipolar transistor shown in FIG. 1. FIG. 4 is a circuit diagram of a memory cell circuit showing another embodiment of the invention. FIG. 5 is a block diagram of a B1C0M5 gate array to which the memory cell circuit shown in FIG. 1 or 4 can be applied. 6th
The figure is a circuit diagram of a conventional NMO3 type memory cell. 7A, 7B, and 7C are circuit diagrams of elements that can be used as the load elements shown in FIG. 6. FIG. 8 is a circuit diagram of a conventional CMO5 type memory cell. In the figure, 5a and 5b are PMOS transistors, 6a
6b is an npn bipolar transistor, 9 is a control terminal,
Vc is an impedance control voltage. 1 figure Vc 50.5b: PMOS) lamp star milk 2 figure vth [V] l Vgs 1 Vc' to, I lb,' PMOS tiger, Shimari 1
2a 12b'. PMOS l-runges 7 13a, 13b: NMO5) runges 14a,
14b pnp 8'' to Borat Oxysister BiCMO8 Kate Are 1 Do U 17A figure 7B figure 7C figure 8 section

Claims (1)

[Claims] An SRAM memory cell circuit having a latch circuit connected to a bit line via an access gate means, the latch circuit being connected in series between first and second power supply potentials. The first
a first inverter means including a load means and a first switching means; a second inverter connected in series between the first and second power supply potentials;
and a second inverter means including a load means and a second switching means, the first and second inverter means being cross-coupled, and the input nodes of the first and second inverter means being ,
The memory cell circuit is connected to a bit line via the access gate means, and the memory cell circuit further includes an impedance that controls the impedance of the first and second load means in response to an operating mode of the memory cell circuit. A memory cell circuit for SRAM including a control means.