JPH04109492A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of malfunction due to the influence of inter-wiring capacity by inputting a positive phase signal and a reverse phase signal to the gate inputs of respective precharging MOS transistors(TRs) and precharging these signals in adjacent signal lines in respectively different periods. CONSTITUTION:A precharging circuit for a dynamic circuit is provided with plural precharge TRs Q5, Q6 connected to a power supply Vcc and is connected to signal lines 5, 6 to be precharged, signals phi1, phi2 are respectively inputted to the gate inputs of the TRs Q5, Q6 as respectively different signals. When the electric charge of one wiring capacitor out of the wiring capacitors C2, C3 of the signal lines 5, 6 to be precharged is discharged, the other capacitor charges electricity by changing the precharging periods of mutually adjacent wirings, the influence of inter-wiring capacity can be removed. Thus, the generation of malfunction due to the influence of inter-wiring capacity can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a dynamic circuit having a precharge circuit.

[Conventional technology]

The precharging method in a conventional dynamic circuit of a semiconductor integrated circuit will be explained with reference to the circuit diagram of FIG. 3 and the waveform diagram of FIG. 4 illustrating its operation.

The configuration of the dynamic circuit shown in FIG. 3 is based on the power supply V. .

The precharge transistor Q! connected to 1Q6, and these precharge transistors Q s ,
A precharge signal φl that controls Q 6 is input to the gate, and an "H" level potential is supplied to signal lines 5 and 6.

Transistors Q + , Q 2 and transistors Q 3 . . . are connected in series to these signal lines 5 and 6, respectively. Q
4 are connected to each other, and transistors Q1 to Q4
The gate inputs are signal 1, signal φ2 . Signal φ2.
Signal 2 is input.

Furthermore, the signal lines 5 and 6 are connected to the positive phase buffers M1. It becomes the input of M2, and outputs the output signal 3.4 of the positive phase buffer M1 and M2.

The operational waveforms of the precharge method in this dynamic circuit are shown in FIG. Here, T + rT3 is the period when the signal φ1 is n level, and T2 + Tt is the period when the signal φ2 is n level.
Indicates the duration of the level.

In period T1 shown in this waveform diagram, precharge signal φ1
Since the transistor Q51Qs is at "H" level, the transistor Q51Qs is turned on and is applied with "H" level potential, charging the wiring capacitances C2 and C3 of the signal lines 5 and 6, respectively, and
6 to the "H" level, and outputs the "H" level to the pressure signals 3 and 4 via the positive phase buffers M1 and M2.

The signal lines 5 and 6 maintain the 'H' level until the next period T2, and in the period T2, the signal φ2 is at the IIH'' level.
Transistors Qz and Qs are turned on, and signals 1 and 2 are each at "H" level.

Since it is at "L" level, transistor Q+ is turned on and transistor Q4 is turned off. At this time, since both transistors Q + and Q 2 are in the on state, the charge in the wiring capacitance jtc2 of the signal line 5 is discharged, and the signal line 5 is set to L.
” level and output signal 3 through positive phase buffer M1.
Outputs “L” level to.

Also, transistor Q3. Since Q is in an on state and an off state, respectively, the potential of the wiring capacitor C3 of the signal line 6 is held, and the positive phase buffer amount 2 output signal 40''H'' level does not change.

The signal lines 5, 6 and the positive-phase buffer output signal 3.4 each hold the "L" level or the "Hn level" until the period T3, and in the period T3, the precharge signal φ1 becomes "H".
'' level, the transistors Q and Qs are turned on, and a potential of H'' level is applied, recharging the wiring capacitances C2 and C3 of the signal lines 5 and 6, respectively, and bringing the signal lines 5 and 6 to the ``H'' level. , outputs "H" level to output signals 3 and 4 via positive phase buffers Ml and M2.

The signal lines 5 and 6 and the positive phase buffer output signal 3°4 maintain the "H" level until the next period T4, and during the period T4,
Since the signal φ2 is at H” level, the transistor Q 2 ,
Q3 is turned on, and since the signal 1.2 is at the low level and high level, the transistor Q1 is turned off and the transistor Q4 is turned on. At this time, since the transistors Q 3 and Q s are both in the on state, the charge in the wiring capacitance C3 of the signal line 6 is discharged, the signal line 6 is brought to the “L” level, and the output signal 4 is outputted via the positive phase buffer M2. Outputs L'' level. Further, since the transistors Q + and Q t are in an off state and an on state, respectively, the potential of the wiring capacitance C2 of the signal line 5 is held, and the "H" level of the positive phase buffer amount 1 output signal 3 does not change.

[Problem to be solved by the invention]

In the precharge circuit in the dynamic circuit of the conventional semiconductor integrated circuit described above, as miniaturization progresses in recent years and the wiring spacing becomes narrower, the capacitance between the wirings increases, and the wiring between the signal lines 5 and 6 in FIG. The space ff1c11 increases significantly. Therefore, when the signal φ2 goes to the "H" level during the period T, the transistors Q, Qs are turned on, and since the signals 1 and 2 are at the "H" level and the "L" level, respectively, the transistors Q is in the on state, and the transistor Q4 is in the off state. At this time, since both transistors Q1 and Q2 are in the on state, the charge in the wiring capacitance C2 of the signal line 5 is discharged, and the signal line 5 is brought to the "L" level. west,
"L" level pressure is applied to the output signal 3 via the positive phase buffer M1. At the same time, the wiring capacitance C3 of the signal line 6 is maintained at H'' level due to the influence of the wiring capacitance C1l even though the transistor Q is in the off state.
When the charge on the signal line 6 is also discharged and the level of the signal line 6 falls below the threshold voltage of the positive phase buffer M2 which inputs the signal line 6, the output signal 4 outputs the 'L' level, as indicated by the dotted line in Fig. 4. F) Malfunctions may occur.

Also, in period T4, when the signal φ2 is at the "H" level, the transistors Q 2 and Q 3 are turned on, and furthermore, since the signals 1 and 2 are at the "L" and "H" levels, respectively, the transistors Q and Q are turned on. Transistor Q4 is in the off state and is in the on state. At this time, transistor Q1
．． Since both Q and Q are in the on state, the wiring capacitance C3 of the signal line 6
The charge is discharged, the signal line 6 is set to "L" level, and the output signal 4 is outputted at "L" level via the positive phase buffer M2. At the same time, the signal line 5 becomes “H” due to the influence of the inter-wiring capacitance C1l even though the transistor Q1 is in the off state.
``The electric charge in the wiring capacitor C2 of the signal line 5 that maintains the level is also discharged, and the level of the signal line 5 decreases, and when it becomes lower than the threshold voltage of the positive phase buffer M1 whose input is the signal line 5, the output signal 3 becomes It outputs the 'L' level, resulting in a waveform shown by the dotted line in FIG. 4, resulting in malfunction.

In the dynamic circuit of this conventional semiconductor integrated circuit, when the precharge signal φ1 is at "H" level, the signal lines 5 and 6 are
charges the wiring capacitances C2 and C3 to reach the "H" level potential, but when the wiring capacitance of one signal line is subsequently discharged to the ground level, only the charge of the wiring capacitance of that signal line is discharged. In addition to discharging, the inter-wiring capacitance C1
This had a great influence in that even the wiring capacitance of the other signal line was discharged. As described above, in the precharge circuit of a dynamic circuit of a semiconductor integrated circuit, there is a drawback that malfunction occurs in the case of parallel wiring having a large inter-wiring capacitance.

An object of the present invention is to solve the above-mentioned drawbacks by precharging the parallel wires in different precharge periods, and to provide a precharge-type dynamic circuit that prevents malfunctions due to the influence of inter-wire capacitance. An object of the present invention is to provide a semiconductor integrated circuit including the following.

[Means to solve the problem]

The structure of the present invention provides a semiconductor integrated circuit having a dynamic circuit in which precharge circuits are provided using MOS transistors on adjacent signal lines wired in parallel on a semiconductor chip.
The present invention is characterized in that a normal phase signal and a negative phase signal are input to the gate inputs of the OS transistors, and the adjacent signal lines are precharged in different periods.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are circuit diagrams showing a part and the whole of an embodiment of the present invention, and FIG. 2 is an operating waveform diagram thereof. This embodiment has a precharge circuit that precharges adjacent signal lines, which are wired in parallel on an IC chip, at different periods.

As shown in the configuration example of FIG. 1(b), the signal lines 19 to 22 to be precharged have precharge transistors Q
,. .about.Q+3 are connected, and all of these precharge transistors Q1.about.Q13 are also connected to the power supply VCC, and the gate inputs of the precharge transistors each receive a signal φ1. Different signals of φ2 are input. Furthermore, after precharging, two transistors Q, , Qts are used to apply data to these signal lines 19 to 22.
: Q...

Qrr*Qrr, Q+s: Q2° and Q2 are connected in series, and the ends of the series connection are grounded. At the same time, data signals 12, 14, 16, 1.8, which input data to the gate inputs of the two transistors connected in series, and control signals 11, 13, 15, 17 which output data to the precharged signal lines. is entered.

The precharge circuit of the dynamic circuit of FIG. 1(b) is connected to the power supply V. 0, and are also connected to signal lines 5 and 6 to be precharged, respectively, and the gate input of the transistor Q5 receives the signal φ1, and the gate input of the transistor Q6 receives the signal φ1. A signal φ2 is input, and each signal is different from the other. Further, transistors Q, , Q2 and transistors Q i , connected in series are connected to the signal lines 5 and 6, respectively.
Q4 are connected to each other, and the ends of the transistors connected in series are grounded. The gate inputs of these transistors Q1 to Q4 are connected to signals 1 and 1, respectively.
Signal φ2. Signal φ1. Signal 2 is being input. Furthermore, the signal lines 5 and 6 are connected to a positive phase buffer Ml.

M2, and is output as the output signals 3 and 4 of the positive phase buffers Ml and M2, and in order to shift this signal 4, the signals φ1. It is output as an output signal 7 via a shift circuit 10 controlled by φ2.

In the period T1 of the waveform diagram in FIG. 2, the signal φ12 and the signal φ2 are at the “H” level and the “IIL” level, respectively, so the transistors Qs and Qs are in the on state, and the transistors Q 2 and
Qa is turned off, and the wiring capacitor C2 is charged with an H level potential on the signal line 5, causing the signal line 5 to become “H” level.
” level and outputs the “H” level to the output signal 3 via the positive phase buffer Ml. On the other hand, the signal line 6 outputs the “H” level to the output signal 3
” level, transistor Q4 is off, and at the same time transistor Q6 is also off, so the wiring capacitance JfLC
Maintaining the charge of 3 and holding the level, the positive phase buffer M2
It outputs to output signal 4 via.

In the next period T2, the signal φ1. Signal φ2 is L”
Since the level is “H” level, the transistor Q! , Q6 is off, transistor Q2゜Ql is on,
The wiring capacitor C3 is charged with an "H" level potential on the signal line 6, and the signal line 6 is brought to an "H" level, and the positive phase buffer M
2, outputs the "H" level to the output signal 4.

On the other hand, in the signal line 5, since the signal is at the "H" level, the transistor Q is turned on, and at the same time, the transistor Q2 is also turned on, thereby discharging the charge in the wiring capacitor C2 and setting the signal line 5 at the "L" level. Output signal 3 via positive phase buffer M1
outputs "L" level.

In the next period T, the signal φ1. Signal φ2 is “H”
Because of the "level uL" level, transistor Q8. Q
s is in the on state, transistor Q2゜Q is in the off state, the wiring capacitor C2 is charged with the charge of the signal line 5 to the "H" level, the signal line 5 is brought to the "H" level, and the positive phase buffer M1 is turned off. The "H" level is output as the output signal 3 through the output signal 3.

On the other hand, on the signal line 6, since the signal 2 is at the "H" level, the transistor Q is turned on, and at the same time, the transistor Q,
Since it is also in the on state, the charge in the wiring capacitor C3 is discharged, the signal line 6 is set to the "L" level, and the output signal 4 is outputted at the "L" level via the positive phase buffer M2. This output signal 4 becomes an input to the shift circuit 10, and the signal φ1 takes in the "H" level of the output signal 4 at the "HI+" level.

Furthermore, in period T4, the signal φl and the signal φ2 are at the "L" level and the "IJH" level, respectively, so the transistor Q
The transistors Q21 and Qs are in the off state, and the wiring capacitance C3 is applied to the signal line 6 at a potential of 'H' level.
, the signal line 6 is set to "H" level, the output signal 4 is outputted to "H" level via the positive phase buffer M2, and the output signal 7 of the shift circuit 10 is taken in during the period T. The "L" level of the output signal 4 is outputted as the "L" level of the output signal 7 when the signal φ2 is at the "H" level. On the other hand, in the signal line 5, since the signal 1 is at the "L" level, the transistor Q1 is turned off, and at the same time, the transistor Q is also turned off, so the charge of the wiring capacitor c2 is maintained and the "H" level is maintained, and the positive phase buffer ° to output signal 3 via Ml
Outputs “H” level.

As explained above, in the precharging method in the dynamic circuit shown in FIG. When the charge of one wiring capacitor is discharged or held at "H" level, the other wiring capacitor is charged, so this embodiment is not affected by the inter-wiring capacitance CI. In this section, we have described the case where there are two signal lines precharged by MOS transistors, but even if the configuration of 0MO8 and P-channel type MO3 transistors or the number of signal lines precharged increases, the number of adjacent wiring lines The influence of inter-wiring capacitance can be easily eliminated by changing the precharge period.

〔Effect of the invention〕

As explained above, in the present invention, after manufacturing a wafer, the precharging period of the signal lines that are wired in parallel and charged is configured to be precharged between different ribs with mutual signals. It has the effect of eliminating

[Brief explanation of the drawing]

1(a) and 1(b) are partial and overall circuit diagrams showing one embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of FIG. 1(a), and FIG. 3 is a conventional circuit diagram. 4 is a circuit diagram showing an example of a dynamic circuit of a semiconductor integrated circuit. FIG. 4 is a waveform diagram showing the operation of FIG. 3. Q+~Qa, Q3-, Qi-, Qto~Qzbee...M
OS transistor, Ml, M2... Positive phase buffer circuit, C1, C11... Inter-wiring capacitance, C2,
C3...Wiring capacitance, φ1. φ2...Clock signal, 1,2゜12.14, 16.18...
...Data signal for inputting data after precharging, 11
, 13, 15. 17... Control signal to output precharged data to the precharged signal line, 2, 5
．． 6... Signal line to be precharged, 3, 4.
...Output signal of positive phase buffer circuit, 7...
・Output signal of shift circuit. Agent Patent attorney Susumu Uchihara +1 □t'v-2 (branch)

Claims (1)

[Claims] In a semiconductor integrated circuit having a dynamic circuit in which precharge circuits are provided using MOS transistors on adjacent signal lines wired in parallel on a semiconductor chip, a positive-phase signal is input to the gate input of the precharge MOS transistor. 1. A semiconductor integrated circuit, wherein a reverse phase signal is inputted, and the adjacent signal lines are precharged in different periods.