JPS6271094A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the loss of a signal voltage of bit lines even if mutual capacity between adjacent bit lines is large by connecting each of two pairs of bit lines to one sense amplifier as input and output signal lines, and at the reading-out of information to one pair of bit signals, holding the other pair of bit signals at a high potential. CONSTITUTION:Before a word line WL1 is turned to the high potential, a control signal phiT2 is turned from the high potential to the low potential. On the other hand, a control signal phiT1 is kept at the high potential as it is. The control signal phiT1 is a control signal for controlling the ON/OFF of transfer gates T1, T3 of a switching circuit 3 connecting bit lines BL1, BL3 to the sense amplifier 2 and also a control signal for controlling the ON/OFF of transistors (TRs) T10, T12. If the control signals phiT2, phiT1 are kept at a low potential and a high potential respectively, the bit lines BL1, BL3 are connected to the sense amplifier 2 and the bit lines BL2, BL4 are kept are precharged status, namely connected to a constant voltage power supply Vcc.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory in which two bit line pairs are connected to one sense amplifier via a switch circuit.

(Conventional technology) Semiconductor mesori has achieved large capacity and high performance by reducing the geometric dimension. If it is applied, the placement resistance increases in proportion to the reciprocal of the reduction rate of the geometric dimension, resulting in performance deterioration.

Furthermore, the situation regarding electromigration becomes severe, which poses a problem in terms of device reliability.

Furthermore, if the interlayer insulating film is made thinner, the risk of short circuits between wiring lines due to pinholes increases. Therefore, a method is generally adopted in which the image is reduced only in the horizontal direction, with almost no reduction in the vertical direction. As this method continues to reduce the size and the vertical and horizontal dimensions of the cross-section of the wiring become approximately the same, the proportion of the mutual capacitance between adjacent wirings in the total linear capacitance increases rapidly. . Therefore, the electric potential of one wiring has a large influence on the electric potential of adjacent wiring.

In the case of semiconductor memories, this problem is particularly noticeable in bit lines. In other words, when a certain word line is selected and information of a memory cell is read out to the bit line, the signal amount on the bit line decreases due to the potential fluctuation of the adjacent WK bit line, resulting in a reduction in the operating margin. It is from.

In order to prevent this, when information from a memory cell is read onto a certain bit line, the potential of the adjacent bit line should not change. In other words, it is sufficient to activate every other bit line.

Conventionally, there has been known a semiconductor memory shown in FIG. 2 in which the bit lines are divided not from this point of view but from the point of view of reducing Cn and 'Cs. (Electronic Materials, Vol. 23, No. 3, 1981, p. 157) As shown in Figure 2,
Two pairs of pins; wire pairs BLI and BL4 and BL2 and BL3
Tora,/Sfutugate Tl, T2, T3,'
Connect to the same sense amplifier 2 via I'4.

When word fitv'L1 is selected, transfer game) T1. T4 becomes conductive, and bit line pair BLx,
BL,i is connected to sense amplifier 2, and so on.

Information on the 1-line pair BLI and BL4 is amplified by the sense amplifier 2. At this time, the bit line pairs BL2 and BL3 are disconnected from the sense amplifier 2.

When the word line WL2 is selected, transfer gates T2 and T3 are conductive, and a pin (line pair BL2, BL) is turned on.
3 are connected to sense amplifier 2, and bit line pair BL2. b
L3c+ information is amplified. Therefore, in this conventional example, every other bit line is activated.

(Problems to be Solved by the Invention) In the conventional semiconductor memory described above, the bit line precharge signal φP is turned off before the word line rises, so the unselected bit line pairs are connected to the constant voltage power supply VCC. It is separated from the body and becomes floating. Therefore, even if every other bit line is activated, the unactivated bit line is in a floating state, so the shielding effect is small, and the signal voltage is affected by the potential change of the single bit line. The disadvantage is that it decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory in which a reduction in operating margin and inversion of information do not occur even when the mutual capacitance between adjacent bit lines occupies a large proportion of the total linear capacitance of the bit lines. .

(Means for Solving the Problems) A semiconductor memory of the present invention has bit lines forming rows, word lines forming columns, and information is transferred between and from the bit lines selected by the word lines. memory cells arranged in rows and columns; and the memory cells arranged in rows and columns.

a sense amplifier in which the first bit i# pair and the second bit line pair of each pair of the tosa serve as input/output signal lines, and each of the first bit line pair a first switch circuit that connects the first bit pair to the sense amplifier when the connected memory cell is selected; and a first switch circuit that connects the first bit pair to the sense amplifier and selects the memory cell connected to each of the $2 bit line pairs. When the second switch circuit connects the second bit line pair to the sense amplifier and the second control signal for the second switch circuit is set to 1.
1. A first precharge circuit that uses the first control signal for the first bit line pair as a precharge control signal for the bit line pair, and a first control signal for the first switch circuit that controls the precharge for the second bit line pair. a second prechy as a control signal;
- a digital circuit.

(Function) The present invention is based on the technical concept of fixing the potential of adjacent bit lines to a constant potential to eliminate the influence of mutual capacitance between adjacent bit lines.

In other words, in a semiconductor memory using a divided bit line system in which every other bit line is activated, adjacent bit lines can be precharged separately, and the potential of an unselected bit line is kept at the precharging level during the read period. 1, and the unselected bit lines have the function of a shield line.

(Example) Next, an example of the present invention will be described with reference to the sections.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The semiconductor memory shown in FIG.
bit lines BLI and BL3 forming a pit line pair, and pit lines #BL2 and B forming a second bit line pair.
L4 and memory cell 1 connected to each bit line j
-1 to 1-4, word lines WL1 to WL4, and transfer gates T! and T3, a second switch circuit 4 including transfer gates T2 and T4, a transistor T9, and
'rti, and a second precharge circuit 6 including transistors TIO and Ti2.

An example will be explained in which the word line WLI is selected at °C in FIG. First, before the word line WLI becomes a high potential, the control signal -T2 is lowered from a high potential to a low potential. The control signal φT2 is a second control signal that controls on/off the transfer circuits T2 and T4 of the second switch circuit 4 that connects the bit line BL2 and the T line BL4 to the sense amplifier 2. 1 precharge circuit 5
Transistor T9 for precharging the bit line BLI of
It is also a control signal for controlling on/off the precharging transistor T'11 of the line BL3. Therefore, by setting the control signal φT2 to a low potential, the bit line BLI and the bit line BL3 are disconnected from the constant voltage power supply V(C), and the bit line BL2 and the bit line BL4 are disconnected from the sense amplifier 2.

On the other hand, the control signal φτ! which is the control signal of Nl! is held at a high potential of 1. The control signal φTt is a signal that controls on/off the transfer circuits TI and T3 of the first switch circuit 3 that connects the bit line BLi and the bit line 13L3 to the sense amplifier 2, and also controls the transfer circuit TI and T3 of the second switch circuit 3 that connects the bit line BLi and the bit line 13L3 to the sense amplifier 2. It is also a control signal that controls on/off the transistor 'I'IO for precharging the bit line BLz of bit line BLz and the transistor T12 for precharging the bit line BL4.

Therefore, the control signal φTt is set to a low potential, and the control signal φT1
By keeping the bit line BLI and bit line BL3 at a high potential, the bit line BLI and bit line BL3 are connected to the sense amplifier 2, and the bit line BL2 and bit line BL4 are in a precharged state, that is, connected to the constant voltage power supply VCC. become in a state of being

In this state, the word line WI,1 becomes high potential, and the information of the memory cell 1=1 is read to the bit line BLI. At this time, as described above, since the adjacent bit lines BL2 are fixed at a constant potential, there is no change in potential even if the mutual capacitance between adjacent bit lines is large, and they are treated as shield lines.

Although Figure 1 shows one seven-pin amplifier, in reality there are many sense amplifiers lined up, and by arranging the human wires in the same way as in Figure 1, it can be activated. There is always a false bit that is fixed at a constant potential next to the edge of the line. This constant potential bit line serves as a shield line, and capacitive coupling between activated bit lines can be ignored. In other words, loss of bit line signal voltage due to mutual capacitance between adjacent wires when information is continuously output from the memory cell is significantly reduced.

When word line WL2 is selected, exactly the same as 1, B's-2 and bit line BI, 4 are activated, n1, ) iBLl and bit line BL3 are held in a precharged state. and the behavior is the same as above.

In addition, in this embodiment, since the precharge control signal and the line switch circuit control signal are also used,
It also has the advantage that the number of wiring lines for tit control signals is reduced by two compared to the conventional example.

(Effect of barking) As explained above, in the semiconductor memory of the present invention, two pairs of bit lines are connected to one sense amplifier as input/output signal lines for each pair, and one bit line pair is connected to one sense amplifier. By keeping the other bit line pair at high 1 when reading information, the loss of bit line signal voltage can be reduced even when the mutual capacitance between adjacent bit lines is large with fewer wires than before. There is.

[Brief explanation of drawings]

The first section is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional semiconductor memory. 1-1. ~, 1-4... Memory cell, 2...
. . . sense amplifier, 3, 4 . . . switch circuit, 5, 60. . ...Precharge circuit, BLI, ~BL4...
・Beep) [, TI, ~, T8...Transfer gate, T9. ~． T12...Transfer resistor, vcc...constant voltage power supply, WLI, ~, WL
4...Word line, φ■, ψIS eφ■2・
...Control signal, φ2...Precharge signal, φSE...Activation signal, φTl +φT2
······Control signal. Agent Patent Attorney Uchihara ; Ben,゛,,l/'

Claims (1)

[Claims] bit lines forming rows, word lines forming columns, memory cells arranged in rows and columns that are selected by the word lines and transfer information to/from the bit lines; A sense amplifier in which a first bit line pair and a second bit line pair each serve as input/output signal lines for each pair, and the memory cell connected to each of the first bit line pairs are selected. a first switch circuit that connects the first bit pair to the sense amplifier when the first pair of bit lines is selected; and a first switch circuit that connects the first bit line to the sense amplifier when the memory cell connected to each of the second bit line pair is selected; a second switch circuit connecting the pair to the sense amplifier;
a first precharge circuit that uses a second control signal for the second switch circuit as a precharge control signal for the first bit line pair; A semiconductor memory comprising: a second precharge circuit that generates a precharge control signal for a second bit line pair.