JPH04109727A - Word identification code error detection circuit - Google Patents

Abstract

PURPOSE:To quickly and easily find out an error in a word identification code by detecting the error automatically when an error takes place in the word identification code. CONSTITUTION:A detection circuit 100 is connected to the error check circuit in order to check an error in a word identification code WI and generates an error check signal DET when the error in the word identification code WI is detected. Moreover, the detection circuit 100 is connected to a measurement device 200 to observe a waveform of the word identification code WI by using an error check signal DET as a trigger. Thus, when an error takes place in the word identification code WI, the detection circuit 100 generates an H level error check signal DRT and it is used as a trigger for the measurement device 200 to observe the waveform of the word identification code WI.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a word identification code error detection circuit, and in particular, to word identification of packet data consisting of a plurality of words that are continuously transmitted in synchronization with a transfer control signal. The present invention relates to a detection circuit for detecting code errors.

[Background Art] In a data processing device or data processing system such as a data flow type information processing device, packet data is transmitted in synchronization with a transfer control signal. If this packet data consists of a plurality of words, a word identification code is given to each word.

Each processing circuit in the data processing device or data processing system identifies which word the word is by this word identification code.

During operation of a data processing device or a data processing system, an error may occur in the word identification code for some reason. If an error occurs in the word identification code, each processing circuit in the data processing device or data processing system malfunctions, so it is necessary to detect the error and investigate the cause of the error. In order to investigate the cause of error occurrence, the waveform of the word identification code at the time of error occurrence is usually observed using a measuring instrument such as a digital oscilloscope or logic analyzer.

[Problems to be Solved by the Invention] However, it is not known when an error in the word identification code will occur, and it is not guaranteed that it will occur. Therefore, in order to investigate the cause of error occurrence, it is necessary to constantly observe the word identification code using a measuring device. Therefore, when an error occurs in the word identification code, it is very difficult to investigate the cause.

An object of the present invention is to provide a detection circuit that can automatically detect an error when it occurs in a word identification code.

[Means for Solving the Problems] A word identification code error detection circuit according to the present invention detects an error in a word identification code of packet data consisting of a plurality of words that are continuously transmitted in synchronization with a transfer control signal. A detection circuit for detecting a signal, comprising a signal generating means and a comparing means. The signal generating means generates a signal corresponding to a normal word identification code in synchronization with the transfer control signal. The comparison means compares the word identification code of the plurality of words with the signal generated by the signal generation means, and outputs an error detection signal when the word identification code and the signal do not match.

[Operation] When transmitting packet data consisting of a plurality of words, the packet data is transmitted sequentially starting from the first word in synchronization with a transfer control signal. Therefore, the word identification code also changes sequentially in response to the transmission of a plurality of words. Therefore, a signal corresponding to a normal word identification code is generated in synchronization with the transfer control signal. By comparing this signal with the word identification code, an error detection signal is output when an error occurs.

This error detection signal can be used as a trigger signal for a measuring instrument.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, a plurality of data transmission lines 1o, 20.30
are connected in series. These data transmission lines 1.0
．． 20.30, packet data is transmitted in order.

Each packet data is transmitted by the first word PD
I and the second word PD2.

The data transmission path 10 includes a data holding circuit 11, a buffer 1
2 and a transfer control circuit 13. Similarly, the data transmission path 20 includes a data holding circuit 21, a buffer 22, and a transfer control circuit 23, and the data transmission path 30 includes a data holding circuit 31, a buffer 32, and a transfer control circuit 33. Each of the transfer control circuits 13, 23, and 33 performs handshake-type transfer control using the transmission permission signal AK and the transfer control signal TC.

Each of the data holding circuits 11, 21, and 31 has a buffer 1
The corresponding transfer control circuit 1 via each of 2.22.32
3.23. Holds the packet data given from the previous stage in synchronization with the transfer control signal TC given from 33,
Output the packet data. In this way, packet data is sequentially transmitted from the data holding circuit at the front stage to the data holding circuit at the rear stage.

The most significant bit of each word applied to each of the data holding circuits 11, 21.31 is used as the word identification code Wl.

In FIG. 1, a detection circuit 100 is connected to detect errors in the word identification code Wl. The detection circuit 100 generates an error detection signal DET when detecting an error in the word identification code WI.

Further, a measuring device 200 for observing the waveform of the word identification code WI using the error detection signal DET as a trigger is connected to the detection circuit 10o.

FIG. 2 is a diagram showing an example of the field configuration of packet data consisting of two words.

The first word PDI of the packet data includes information such as an operation code and a node number, and has a word identification code WI set in its most significant bit. The second word PD2 of the packet data includes data, and the word identification code Wl is set in its most significant bit. For example, the word identification code WI of the first word PDI is set to "1", and the word identification code WI of the second word is set to "0".

FIG. 3 is a circuit diagram showing the configuration of the detection circuit 100 shown in FIG. 1.

Detection circuit 100 includes inverters 1, 6, and 7, D-type flip-flops 2, 4.5, and exclusive OR gate 3.

A transfer control signal TC is applied to the input terminal of the inverter 1, and a word identification code WI is applied to one input terminal of the gate 3.
is given. In the embodiment shown in FIG. 1, the detection circuit 100 includes a transfer control signal TC output from the data transmission path
and a word identification code WI. Inverter 1
The output of flip-flop 2 and flip-flop 5
is applied to the clock input terminal CK of. The output from the inverting output terminal Q of the flip-flop 2 is given to the input terminal. The output signal a from the output terminal Q of the flip-flop 2 is applied to the other input terminal of the gate 3. A power supply voltage V is applied to the set terminal S of the flip-flop 2. 0 is given, and a mask reset signal MR is given to the reset terminal π. Flip-flop 2 divides the inverted signal of transfer control signal TC by two. As a result, the output signal a becomes a signal corresponding to a normal word identification code.

The output signal of gate 3 is applied to the input terminal of flip-flop 4. On the other hand, the input terminal of the flip-flop 5 is grounded. Output terminal Q of flip-flop 5
The output signal is passed through the inverter 6.7 to the set terminal S and the clock terminal C of the flip-flop 4 as a signal C.
given to K.

The reset terminal 100 of the flip-flop 5 has a power supply voltage vD.
D is given. A delay occurs between the determination of the transfer control signal TC and the determination of the word identification code WI. Therefore, the output signal of the inverter 1 is delayed by the flip-flop 5 and the inverter 6.7, and the delayed signal C is provided as a signal to the flip-flop 4.

The set terminal 100 of flip-flop 4 has a power supply voltage vDo.
is given to the reset terminal R, and the mask reset signal ■
is given.

The output from the output terminal Q of the flip-flop 4 is used as the detection signal DET.

Next, the operation of the detection circuit shown in FIG. 3 will be explained with reference to the timing chart shown in FIG. 4.

Transfer control signal TC is active L''.

Also, flip-flop 2. 4. 5 holds the input signal at the input terminal in response to the rise of the input signal at the clock terminal CK, and outputs the input signal from the output terminal Q. The output signal of the inverted output terminal is the inverted signal of the output signal of the output terminal Q.

In the initial state, the mask reset signal MR is set to “
It falls to "L" and then returns to "H".Thereby, the output signal of the inverted output terminal of the flip-flop 2 is "H".

First, when the transfer control signal TC falls to "L", the input of the clock input terminal CK of the flip-flop 2 rises to "H" by the inverter 1.

As a result, the output signal a of flip-flop 2 becomes “H”.
stand up. At the same time, the output signal of the inverting output terminal Q of the flip-flop 2 falls to "L".

After the transfer control signal TC rises to “H”, it then rises to “L”.
When the transfer control signal TC falls to "L", the output signal a of the flip-flop 2 falls to "L". In this way, every time the transfer control signal TC falls to "L", the output signal a of the flip-flop 2 falls to "H". It changes alternately like "L", "H", "L", etc.

On the other hand, when the word identification code WI is normal, the word identification code WI alternately changes to "H", "L", "L", etc. in response to the falling of the transfer control signal TC. Change. However, the change in the word identification code WI is delayed by a certain period of time from the fall of the transfer control signal TC.

The gate 3 compares the word identification code Wl with the output signal a, and if they match, the output signal is set to "L", and if they do not match, the output signal is set to "H".
shall be.

However, since a certain delay occurs between the word identification code WI and the transfer control signal TC, the word identification code W
Even if (2) is normal, the output signal remains "H" for a certain period of time. Therefore, the output signal of the gate 3 is applied to the flip-flop 4, and the output signal of the inverter 1 is delayed by a certain period of time.
After , flip-flop 4 is triggered. As a result, if the word identification code Wl and the signal a match, the error detection signal DET becomes 'L'.The word identification code Wl
If the transfer control signal TC and the transfer control signal TC do not match, the error detection signal DET becomes "H".

In this way, when an error occurs in the word identification code WI, the detection circuit 100 outputs the error detection signal DE of "H".
Since the error detection signal DET is generated, the waveform of the word identification code WI can be observed by using the error detection signal DET as a trigger for the measuring device 200 shown in FIG.

Although the above embodiment describes the case where the packet data consists of two words, errors in the word identification code can be detected in the same way even when the packet data consists of three or more words. be. Even when the packet data consists of 3 words or more, a signal corresponding to a normal word identification code is generated based on the transfer control signal TC, the signal is compared with the word identification code, and an error is detected based on the comparison result. Output a signal.

[Effects of the Invention] As described above, according to the present invention, when an error occurs in a word identification code, this error can be automatically detected, so that errors in the word identification code can be discovered quickly and easily. This makes it possible to investigate the cause of the problem. Therefore, the debugging period can be significantly shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. FIG. 2 is a diagram showing an example of the field structure of each word of packet data transmitted in the embodiment of FIG. 1. FIG. 3 is a circuit diagram showing the configuration of the detection circuit. FIG. 4 is a timing chart for explaining the operation of the detection circuit of FIG. 3. In the figure, 1.6.7 is the inverter, 2.4°5 is D
type flip-flop, 3 is exclusive OR gate, 1
0.20.30 is a data transmission path, 100 is a detection circuit, 2
00 indicates a measuring device, TC indicates a transfer control signal, Wl indicates a word identification code, PDI indicates the first word of packet data, and PD2 indicates the second word of packet data. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 4 Patent Applicant Sharp Corporation

Claims (1)

[Claims] A detection circuit for detecting an error in a word identification code of packet data consisting of a plurality of words continuously transmitted in synchronization with a transfer control signal, the detection circuit detecting an error in a word identification code of packet data consisting of a plurality of words transmitted continuously in synchronization with a transfer control signal, the detection circuit detecting an error in a word identification code in synchronization with the transfer control signal. a signal generating means for generating a corresponding signal; and comparing a word identification code of the plurality of words to be transmitted with the signal generated from the signal generating means;
A word identification code error detection circuit, comprising: comparison means for outputting an error detection signal when the word identification code and the signal do not match.