JPH0411133B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a counting circuit that can be used as various measuring means.

"Background of the Invention" Measurement systems that capture various phenomena as electrical signals, convert the electrical signals into pulse signals, count the pulse signals, and cumulatively add the counted values are widely used.

In such a measurement system, when the measurement time is continuously long, the count value of the counter is extracted as necessary, and various controls or processes are performed using the extracted count value.
Conventionally, in order to take out the counted value of the counter as necessary, a method has been adopted in which a memory is attached to the counter, and a latch signal is applied to the memory to read the counted contents of the counter at that time.

"Prior Art" FIGS. 4 and 5 show conventional counting circuits. In the example shown in FIG. 4, two counters, 1A and 1B, are provided, and these two counters 1A and 1B are operated alternately every time a read request is issued, and when a read request is issued, the counters 1A and 1B are operated alternately. The system is configured so that the counter that has been in use is stopped, a latch signal is given to the memory 2A or 2B attached to that counter, and the count value of the counter is read into the memory. Note that 3 indicates an input signal and 4 indicates a read request signal. Further, 5 is a switching control signal generator, 6A and 6B are signal switchers, and 7A and 7B are delay circuits, respectively.

The example in FIG. 5 shows a counting circuit proposed in ``Japanese Unexamined Patent Publication No. 60-51026.'' The counting circuit described in this publication divides the counter 1 into a high speed counter 1H and a low speed counter 1L, and when a read request signal 4 is input, a latch signal generator 8 waits for the input signal to rise and generates a latch signal 9. generate,
The latch signal 9 is passed through the delay circuit 7 to the memory 2.
A case where the configuration is given to A and 2B is shown.

Furthermore, as proposed in Japanese Patent Application Laid-Open No. 57-194636, the count value of a counter is transferred to an intermediate memory that latches in synchronization with this counter, and the count value transferred to this intermediate memory is transferred to an arbitrary memory. A configuration in which the data is read into the second digital circuit at the time is also conceivable.

However, when configured in this way, an intermediate memory that operates at the same speed as the counter is required, especially when the counter counts at high speed.
Since the intermediate memory is also required to operate at high speed, it has the disadvantage that an expensive latch circuit element must be used as the intermediate memory.

``Problems to be Solved by the Invention'' According to the structure shown in FIG. 4, two counters, 1A and 1B, are required, which increases the circuit size and makes it expensive. Furthermore, each time the read request signal 4 is given, the two counters 1A and 1B alternately go into the hibernation state, so a counting error of ±count occurs when entering the hibernation state and when returning from the hibernation state to the operating state. However, the disadvantage is that the counting errors accumulate.

In the example shown in FIG. 5, the counter 1 performs a continuous counting operation, so that the disadvantage of a ±1 count error is eliminated.

However, in this structure, the memory devices 2A and 2
As shown in FIG. 6, the generation of the latch signal 9 is delayed by the period P from when the read request signal 4 is issued until the rising edge of the input signal 3 input next, as shown in FIG. 6, and the latch operation is delayed. is made to wait.

For this reason, there is no particular problem when the input signal is a pulse with a relatively fast period, but when the repetition interval of the input signal is relatively long and the occurrence is random,
Even if the read request signal 4 is applied, a problem arises in that the true count value at that time cannot be obtained immediately.

"Means for Solving the Problem" In the present invention, in a counting circuit of a type in which a memory is attached to a counter and the count value of the counter is taken into the memory and read out, a path for a read request signal to be supplied to the memory is provided. At the same time, a latch inhibiting means is provided to prevent the read request signal from passing for the time required for the counter to transition from the trigger edge of the counter, and when the read request signal is inhibited by the latch inhibiting means, the counter is reactivated when the inhibition is released. The structure includes an internal latch signal generating means for providing a latch signal.

According to the configuration of the present invention, even if the read request signal is input at the time when the input signal is input to the counter or while the state of the counter is changing after the input signal is input, the latch inhibiting means prevents the read request signal from being output. Prevent it from being entered into the memory. When the inhibited state is released, the internal latch signal is output again from the internal latch generating means and applied to the memory. Therefore, even if a read request signal is issued during the inhibit period, the latch operation is performed with a slight delay, and the count value at that time can be output.

Note that if the read request signal is applied during a period other than the inhibit period, the latch operation is performed immediately at that time.

As described above, according to the present invention, the true count value at that point in time can be read out immediately in response to the read request signal, except for the transition period of the counter. However, since the latch operation is performed except during the transition period of the counter, the counted value can be loaded into the memory without causing an error of ±1 count.

Furthermore, since the counter is not stopped each time a read request is made, an error of ±1 count will not be accumulated in the count value of the counter. Therefore, the true count value at the time of the read request can be read accurately and without time delay, which provides an advantage.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In this invention, a memory device 2 is attached to the counter 1, and by giving a read request signal to the memory device 2, the count value of the counter 1 is taken into the memory device 2, and this count value is read out from the memory device 2. In the counting circuit configured as above, a latch inhibiting means 12 is provided on the common path 11 of the read request signal 4 to prevent passage of the read request signal 4 while the counter 1 is in transition, and together with this, the read request signal 4 is disabled during the latch inhibit period. An internal latch signal generating means 13 is provided for applying a latch signal to the memory device 2 again when the inhibited state of the latch inhibiting means 12 is released when the signal is applied. Reference numeral 14 indicates a reset signal generating means for resetting the internal latch signal generating means 13.

In this example, the latch inhibiting means 12 is connected to the inverter 1.
2A, delay circuit 12B, and NAND gate 12C
A case is shown in which the circuit is configured by an AND gate 12D. The inverter 12A inverts the polarity of the input signal 3, and the inverted signal is delayed by the delay circuit 12B. The delay amount τ of the delay circuit 12B is set to be equal to or slightly longer than the time required for the transition of the counter 1.

The input signal 3 is applied to one input terminal of the NAND gate 12C, and the inverter 12 is applied to the other input terminal.
A and the signal 15 through the delay circuit 12B (Fig. 2B)
reference). As a result, as shown in FIG. 2C, the NAND gate 12C outputs a signal 16 which becomes L logic from the rise of the input signal 3 to the delay time τ of the delay circuit 12B. This signal 16 is applied to one input terminal of the AND gate 12D, and the AND gate 12D is controlled to be closed for a period of time τ. The read request signal path 11 is controlled to be closed for a period of time .tau. from the trigger edge of the counter 3 (rising edge of the input signal) to prevent the read request signal 4 from passing through.

The output signal of the AND gate 12D is applied to the internal latch signal generating means 13 as the output signal of the latch inhibiting means 12. Internal latch signal generating means 13
In this example, an R-S flip-flop is used. The output signal of the latch inhibiting means 12 is R-S.
The output signal of the reset means 14 is applied to the set terminal S of the flip-flop, and the output signal of the reset means 14 is applied to the reset terminal R.

The output signal 17 of the internal latch signal generating means 13 is applied to the latch input terminal of the memory 2.

In such a configuration, the read request signal 4 is
As shown in the first half of the time axis of the figure, the rat prohibition period τ
If it is input in a period Q other than (E in Figure 2),
During this period Q, the signal 16 input to the AND gate 12D is at H logic, so the read request signal 4
passes through the latch inhibiting means 12 and is applied to the internal latch signal generating means 13. The internal latch signal generating means 13 is triggered by the rising edge of the read request signal 4, and outputs the internal latch signal 17 shown in FIG. 2F.

This internal latch signal 17 is applied to the latch input terminal of the memory 2, and when it rises, the memory 2
the latest count value of counter 1 at that point
Take in D ₁ .

On the other hand, if the read request signal 4 is input during the latch inhibit period τ as shown in the latter half of the time axis in FIG. 2E, the read request signal 4 is prevented from passing by the latch inhibit means. . When the latch inhibiting period τ has elapsed and the latch inhibiting state is released, the inputs of the AND gate 12D constituting the latch inhibiting means 12 both become H logic, and the output thereof outputs H logic. The rising edge of this H logic triggers the internal latch signal generating means 13 to output the internal latch signal 17A.

The internal latch signal 17A rises at a timing when the latch prohibition time τ has elapsed. In other words, after the state of counter 1 changes, the count contents change to
This is when it was confirmed as Dn. Therefore, the memory 2 takes in the count content Dn of the counter 1 immediately after the transition. Note that the internal latch signal generating means 13 is reset at the next fall of the signal 16 after the read request signal 4 returns to L logic.

``Operations and Effects of the Invention'' As explained above, according to the present invention, the counted contents of the counter 1 are immediately transferred to the memory 2 as soon as the read request signal 4 is applied, except for the transition period of the counter 1 (equivalent to the latch inhibit period τ). can be taken into account.

Also, during the transition period of counter 1, read request signal 4
If , the count contents of counter 1 are taken into memory 2 at the time when the transition of counter 1 is completed.

Therefore, even if the input signal 3 is a random pulse as shown in FIG. 3A, and the time interval is relatively long, there is no significant delay from the rise of the read request signal 4, that is, there is a delay corresponding to the delay in the operation of the flip-flop. Then, the internal latch signal 17 (FIG. 3D) is output, and the latest count value _D1 at that time can be taken into the memory 2 as shown in FIG. 3E.

Further, according to the present invention, data is not taken into the memory 2 during the transition period of the counter 1, so that a counting error of ±1 count is not taken in. However, since the counter 1 performs a continuous counting operation, the count value of the counter 1 does not accumulate a count value of ±1.

Therefore, in response to a read request, there is an advantage that the latest counting contents at the time of the request can be read out without time delay.

Furthermore, in this invention, the count contents of the counter 1 are directly read into the memory device 2, and there is no need to interpose an expensive latch circuit element between the counter 1 and the memory device 2, so that the overall manufacturing cost can be reduced. You also get the advantage of being able to.

In the above description, the internal latch signal generating means 13 is set to R-.
Although an example using an S flip-flop has been described, other examples such as a D-type flip-flop or a J-K flip-flop can also be used.
It can also be constructed using flip-flops.

Also, although we have explained an example in which the counter 1 is not divided into a high speed side (lower digit side) and a low speed side (above digit side), as shown in Figure 5, it is divided into a high speed side and a low speed side, and these are connected in cascade. The present invention can also be applied to counters of this type.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a waveform diagram for explaining the operation of this invention, FIG. 3 is a waveform diagram for explaining the effects of this invention, and FIG. 4 is a waveform diagram for explaining the effects of this invention. 5 is a block diagram for explaining the prior art, and FIG. 6 is a waveform diagram for explaining the drawbacks of the prior art. 1: Counter, 2: Memory device, 3: Input signal,
4: Read request signal, 11: Read request signal path, 1
2: Latch inhibiting means, 13: Internal latch signal generating means, 14: Resetting means, 17, 17A: Internal latch signal.

Claims (1)

[Scope of Claims] 1. A counter that counts input signals; B. A memory that latches the counted value of this counter; and C. latch inhibiting means for blocking passage of the read request signal for the time required for the transition of D; a read request signal is applied through this latch inhibiting means, and if the latch inhibiting means is in a non-inhibited state, the rising edge of the read request signal is Immediately give a latch signal to the memory device in synchronization, and
When the read request signal is applied while the latch inhibiting means is in the latch inhibited state, internal latch signal generating means provides a latch signal to the storage device when the latch inhibiting means releases the inhibition, and a counting circuit comprising: .