JPH042505Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an error counting and alarm issuing circuit in a transmission line.

〔overview〕

Equipped with a K-stage shift register, an error alarm counts error pulses each time an error pulse is input, stores the number of errors, and issues an alarm when error pulses occur N times in a row in a predetermined period. By providing a flip-flop circuit in the circuit that initializes the shift register of the error pulse counting circuit every time the oscillator clock pulse is input, an error alarm circuit with a simple circuit configuration that does not require a trigger pulse circuit is realized. .

[Conventional technology]

As a method of counting errors in the transmission path and issuing an alarm, K (positive integer) or more error pulses are counted during time T, and if this state continues N (positive integer) times, an alarm is issued. There is a method to issue. This conventional error alarm circuit has a circuit configuration shown in FIG.

FIG. 3 is a block diagram of a three-stage error alarm circuit that issues an alarm when three or more error pulses are counted three times in a row during a certain period of time T.

The trigger pulse circuit 5 is composed of an AND gate 54 which takes the logical product of the output of an oscillation circuit 51 that generates a pulse with a period T and the output that is passed through a delay circuit 52 and inverted by an inversion circuit 53. , generates a thin pulse every period T. The error pulse counting circuit 1 includes three stages of shift registers 11, 12,
13, and when three or more error pulses are counted during the period T, the output Q3 of the third stage shift register ₁₃ of the error pulse counting circuit 1 changes from low level to high level. The error pulse counting circuit 1 is returned to its initial state by a thin pulse obtained by inverting the output of the trigger pulse circuit by an inverting circuit 6.

The alarm issuing circuit 2 includes a three-stage shift register 21,
22, 23 and their outputs Q ₄ , Q ₅ , Q ₆ , and when a thin pulse from the trigger pulse circuit enters, the output Q ₃ of the third stage shift register 13 of the error pulse counting circuit 1 is output. The state of is stored as the Q output of the three stages of shift registers 21, 22, and 23, and when the output _Q3 of the third stage of the shift register of the error pulse counting circuit 1 is at high level three times in a row, the logical product is emits an alarm pulse as an output.

[Problem that the invention attempts to solve]

The conventional error alarm circuit described above requires a trigger pulse circuit that stores the output of the error pulse counting circuit in the shift register of the alarm issuing circuit and generates a thin pulse at a period T to return the error pulse counting circuit to its initial state. Therefore, the error alarm circuit becomes complicated and large, and since the trigger pulse circuit uses a delay circuit, it is difficult to integrate it into an integrated circuit.

An object of the present invention is to provide an error alarm circuit that has a simple circuit configuration that does not require a trigger pulse circuit and is suitable for integration into an integrated circuit.

[Means for solving problems]

The present invention counts the error pulses and calculates K (positive integer)
When more than one error pulse is counted, an error pulse counting circuit including a K-stage shift register that changes the state and the output state of this error pulse counting circuit are stored, and In an error alarm circuit comprising an alarm generation circuit that sends out an alarm pulse when the output of the error pulse counting circuit changes, and an oscillation circuit that generates a pulse with a period T, the output pulse of the oscillation circuit is used as a clock input and the output pulse of the oscillation circuit is used as a clock input. The present invention is characterized in that it includes a flip-flop circuit that sends out an output pulse to initialize each stage of the shift register of the error pulse counting circuit.

Furthermore, the output of the first stage of the shift register of the error pulse counting circuit is input to the set or reset terminal of the flip-flop circuit, so that when a clock pulse is input to the flip-flop circuit, the shift register of each stage of the error pulse counting circuit is initialized. It is preferable that the configuration is such that the state is set.

[Effect]

The flip-flop circuit returns to its initial state at the rising edge of the clock pulse with period T, is set or reset by the output of the first stage of the shift register of the error pulse counting circuit, and is reset by the input of the next clock pulse to the shift register of the error pulse counting circuit. Return to initial state. If K or more error pulses are counted before the next clock pulse of period T is input, that state is stored in the alarm issuing circuit, and when that state is counted N times in succession, an error alarm is issued.

〔Example〕

Next, the present invention will be explained with reference to the drawings.
FIG. 1 is a block diagram of a first embodiment of the present invention. FIG. 1 is an example of a three-stage error alarm circuit.

This circuit consists of an oscillation circuit 3 that outputs pulses with period T, an error pulse counting circuit 1 consisting of three stages of shift registers 11, 12, and 13, three stages of shift registers 21, 22, and 23, and their respective outputs _Q4. ，
An alarm issuing circuit 2 consisting of a logical product 24 of Q ₅ and Q ₆ ;
It is constituted by a flip-flop 4 which returns the error pulse counting circuit 1 to its initial state at the rising edge of the output pulse of the oscillation circuit 3.

Next, the operation of this embodiment will be explained.

In the initial state in which the outputs Q ₁ , Q ₂ , and Q ₃ of the three-stage shift register of the error pulse counting circuit 1 are at a low level, the output Q ₇ of the flip-flop 4 becomes a high level, and the error pulse counting circuit 1 is released from the reset state. . In this state, when an error pulse is input, the output _Q1 of the shift register 11 of the error pulse counting circuit 1 becomes high level, and at the same time, the set terminal S of the flip-flop 4 also becomes high level, and the flip-flop 4 is set.

When the output pulse of the oscillator circuit 3 rises with the flip-flop 4 set, the output _Q7 of the flip-flop 4 becomes low level.
3-stage shift register 1 of error pulse counting circuit
The outputs Q ₁ , Q ₂ , Q 3 of flip-flops 1, 12, _{and 13} are reset to low level, and at the same time, the set terminal S of flip-flop 4 becomes low level, and the output Q ₇
becomes high level and the error pulse counting circuit 1
Released from reset state.

If three or more error pulses are counted before the rising edge of the output pulse of the oscillation circuit 3 enters the flip-flop 4, the output Q3 of the third stage shift register ₁₃ of the error pulse counting circuit 1 becomes high level.
In this state, when the rising edge of the output pulse of the oscillation circuit 3 is input to the flip-flop 4, the state of the output _Q3 of the shift register 13 is stored as the output _Q4 of the shift register 21 of the alarm issuing circuit 2, and at the same time, the error pulse counting circuit 1 The three stages of shift registers 11, 12, and 13 return to their initial states. In this manner, when three or more error pulses are counted three times in a row during the period T, an alarm pulse is issued as the output of the AND 24 of the alarm issuing circuit 2.

FIG. 2 is a diagram showing another embodiment of the present invention, in which the output of the first stage shift register 11 of the error pulse counting circuit 1 is input to the reset terminal of the flip-flop 4, and the inverted output is input to the reset terminal of the flip-flop 4. 1 is input to the reset terminal of each shift register. In this embodiment, as in the embodiment shown in FIG. 1, the inverted output _Q8 of the flip-flop 4 becomes low level at the rising edge of the output pulse of the oscillation circuit 3, and the shift registers 11, 12, 13 of the error pulse counting circuit 1 are set to the initial state. Return to

Although the above embodiment shows an example in which the shift register has three stages, it is natural that the shift register of the error pulse counting circuit can generally be constructed in K stages.

[Effect of idea]

As explained above, the present invention provides the function of returning the error pulse counting circuit to its initial state at the rising edge of the output pulse of the oscillation circuit, thereby reducing the period T.
Since there is no need for a trigger pulse circuit that generates a narrow pulse, the circuit becomes simple, and since a delay circuit is not required, it is suitable for integration into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. Second
The figure is a block diagram of another embodiment of the present invention. FIG. 3 is a block diagram of a conventional example. 1...Error pulse counting circuit, 2...Alarm issuing circuit, 3...Oscillation circuit, 4...Flip-flop,
5...Trigger pulse circuit, 11, 12, 13, 2
1, 22, 23...Shift register.

Claims (1)

[Claims for Utility Model Registration] (1) An error pulse counting circuit 1 including a K-stage shift register that counts error pulses and changes its state when K (positive integer) or more error pulses are counted. , an alarm generation circuit 2 that stores the output state of the error pulse counting circuit and sends out an alarm pulse when the output of the error pulse counting circuit changes N (positive integer) times in succession; and a pulse with a period T. The error alarm circuit includes an oscillation circuit 3 which generates an error pulse, and a flip-flop circuit 4 which uses the output pulse of the oscillation circuit as a clock input and sends out an output pulse that initializes each stage of the shift register of the error pulse counting circuit. An error alarm circuit comprising: (2) The flip-flop circuit 4 has a configuration in which the output of the first stage of the shift register of the error pulse counting circuit is used as a set input, and the output thereof is input to the reset terminal of the shift register of each stage of the error pulse counting circuit. An error alarm circuit according to claim (1) of patent registration. (3) The flip-flop circuit 4 has a configuration in which the output of the first stage of the shift register of the error pulse counting circuit is used as a reset input, and its inverted output is input to the reset terminal of the shift register of each stage of the error pulse counting circuit. Scope of claim for utility model registration No.
The error alarm circuit described in paragraph (1).