JPH04112596A - Manufacture of multilayer printed wiring board - Google Patents

Manufacture of multilayer printed wiring board

Info

Publication number
JPH04112596A
JPH04112596A JP2231739A JP23173990A JPH04112596A JP H04112596 A JPH04112596 A JP H04112596A JP 2231739 A JP2231739 A JP 2231739A JP 23173990 A JP23173990 A JP 23173990A JP H04112596 A JPH04112596 A JP H04112596A
Authority
JP
Japan
Prior art keywords
layer
circuit conductor
wiring board
layers
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2231739A
Other languages
Japanese (ja)
Inventor
Hisashi Nakamura
中村 恒
Hiroshi Hasegawa
洋 長谷川
Yasuto Isozaki
康人 礒崎
Hiroshi Sogo
十河 寛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2231739A priority Critical patent/JPH04112596A/en
Publication of JPH04112596A publication Critical patent/JPH04112596A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は広範な電子機器に用いられる多層プリント配線
板の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing multilayer printed wiring boards used in a wide variety of electronic devices.

従来の技術 近年、電子機器の小型計量化や高機能化、高性能化に対
する要求か増加するにつれ、多層プリント配線板の需要
か著しく増加している。
BACKGROUND OF THE INVENTION In recent years, as the demand for smaller size, higher functionality, and higher performance of electronic equipment has increased, the demand for multilayer printed wiring boards has increased significantly.

従来の多層プリント配線板はいろいろな方法により作ら
れているか、その代表的製造方法として6層の多層プリ
ント配線板を例にとりその製造工程を第2図A、Bに示
した。
Conventional multilayer printed wiring boards are manufactured by various methods. As a typical manufacturing method, a six-layer multilayer printed wiring board is taken as an example, and its manufacturing process is shown in FIGS. 2A and 2B.

第2図A、Hにおいて、la、lbは絶縁基板、2a、
2a’ 、2b、2b’ は内層回路導体層、3a、3
b、3cはプリプレグ絶縁層、4a4bは金属銅箔、5
は貫通孔、6a、6bは最外層回路導体層である。
In FIGS. 2A and 2H, la and lb are insulating substrates, 2a,
2a', 2b, 2b' are inner circuit conductor layers, 3a, 3
b, 3c are prepreg insulating layers, 4a4b are metal copper foils, 5
is a through hole, and 6a and 6b are outermost circuit conductor layers.

この6層の層数を有する多層プリント配線板は一般にガ
ラスエポキシ積層板等の絶縁基板1a1bの表裏両面に
それぞれ金属銅箔を接着した所謂銅張り積層板を使用し
て、先ずフォトエツチング法によって絶縁基板1a、l
bの表裏面にそれぞれ必要とする内層回路導体層2a、
2a  及び2b、2b’ を形成し、この2枚の内層
回路形成基板を第2図Aに示すように3枚のブリブレク
絶縁シート3a、3b、3cを介在させてさらに最外層
に金属銅箔4a、4bを積み重ね、熱プレスにより加圧
加熱してプリプレグ絶縁層3a、3b3cを硬化して一
体成型する。その後に第2図Bに示すように必要な箇所
に貫通孔5をあけ、無電解銅めっきと電解銅めっきを併
用して最外層の金属銅箔4a、4bの表面と貫通孔5の
内壁面に金属銅を析出させる。しかる後にフォトエツチ
ング法によって金属銅箔4a、4bのうち不要な金属銅
層を除去し、スルーホール導体層を通して内層回路導体
層2a、2a’ 、2b、2b’ と電気的に接続した
最外層の回路導体層6a、6bを形成する。
This multilayer printed wiring board having 6 layers generally uses a so-called copper-clad laminate in which metal copper foil is adhered to both the front and back sides of an insulating substrate 1a1b such as a glass epoxy laminate, and is first insulated by photo-etching. Substrates 1a, l
Required inner circuit conductor layers 2a on the front and back surfaces of b,
2a, 2b, 2b' are formed, and these two inner layer circuit forming boards are interposed with three BRIBREK insulation sheets 3a, 3b, 3c as shown in FIG. , 4b are stacked, and the prepreg insulating layers 3a, 3b3c are cured and integrally molded by heating under pressure using a hot press. Thereafter, as shown in FIG. 2B, through-holes 5 are made at necessary locations, and electroless copper plating and electrolytic copper plating are combined to coat the surfaces of the outermost layer metal copper foils 4a and 4b and the inner wall surface of the through-holes 5. Metallic copper is deposited on the surface. Thereafter, unnecessary metal copper layers of the metal copper foils 4a and 4b are removed by photoetching, and the outermost layer is electrically connected to the inner circuit conductor layers 2a, 2a', 2b, and 2b' through the through-hole conductor layers. Circuit conductor layers 6a and 6b are formed.

発明が解決しようとする課題 しかしながら上述した従来例による多層プリント配線板
は内層回路導体層2a、2a’ 、2b2b’相互の電
気的接続は全て貫通孔5を導通化するスルーホール接続
法によって行われるために、層数か増大するにつれて各
層の回路導体層を接続するための貫通孔の数か多くなる
。従って基板面積に占める貫通孔の占有面積か大きくな
ることにより回路設計の自白度か制約され、結果的に回
路の高密度化かはかりにくくなる。またスルーホール接
続の場合、孔加工工程で発生ずるスミア−の影響を受け
て回路導体層間の電気的接続の信頼性か乏しくなるとい
う欠点かあった。また方、従来例の多層プリント配線板
では層間絶縁層にガラス繊維にエポキシ樹脂を食潰した
分厚いンート状のプリプレグ材を使用しているために、
積層した多層プリント配線板全体の薄型化かはかりにく
いという問題点を有していた。
Problems to be Solved by the Invention However, in the multilayer printed wiring board according to the conventional example described above, the mutual electrical connections between the inner circuit conductor layers 2a, 2a', 2b2b' are all performed by a through-hole connection method in which the through holes 5 are made conductive. Therefore, as the number of layers increases, the number of through holes for connecting the circuit conductor layers of each layer increases. Therefore, as the area occupied by the through holes in the board area increases, the degree of clarity of circuit design is restricted, and as a result, it becomes difficult to measure whether the circuit can be made denser. Further, in the case of through-hole connection, there is a drawback that the reliability of the electrical connection between the circuit conductor layers becomes poor due to the influence of smear generated during the hole processing process. On the other hand, in conventional multilayer printed wiring boards, the interlayer insulating layer uses a thick prepreg material made of glass fiber and epoxy resin.
There was a problem in that it was difficult to measure the thickness of the entire laminated multilayer printed wiring board.

本発明は、−り記問題点を解決するもので、貫通孔の占
有面積の小さく、薄型化を図る多層プリント配線板を提
供することを目的とする。
The present invention solves the above-mentioned problems, and aims to provide a multilayer printed wiring board in which the area occupied by through holes is small and the thickness of the board is reduced.

課題を解決するだめの手段 この目的を達成するために本発明は、絶縁基板の表裏両
面それぞれに回路導体層と絶縁樹脂層を交互に形成しか
つ前記絶縁基板の貫通孔及び絶縁樹脂層に設けたブライ
ンドバイヤホールを通して回路導体層相互か電気的に接
続するように任意の層数の内層配線基板を構成し、前記
内層配線基板の表裏両面層に接着剤層を介して金属銅は
くを接着し、その後にフォトエツチング法によって前記
内層回路導体層と電気的に接続される最外層の回路導体
層を形成するものである。
Means for Solving the Problems In order to achieve this object, the present invention provides circuit conductor layers and insulating resin layers that are alternately formed on each of the front and back surfaces of an insulating substrate, and provided in the through holes of the insulating substrate and the insulating resin layer. An inner layer wiring board having an arbitrary number of layers is constructed so that the circuit conductor layers are electrically connected to each other through blind via holes, and metal copper foil is bonded to both the front and back layers of the inner layer wiring board via an adhesive layer. Thereafter, an outermost circuit conductor layer electrically connected to the inner circuit conductor layer is formed by photoetching.

作用 これにより、内層回路導体層相互か貫通孔のみによる接
続形態をとることかなくなるので、貫通孔の孔数か減少
して回路の高密度化がはかれると共に層間回路導体層間
の電気的接続の信頼性が向上し、さらには層間絶縁層に
プリプレグ絶縁ノートを使用しないため薄型化か実現さ
れることとなる。
As a result, it is no longer necessary to connect the inner circuit conductor layers to each other using only through holes, thereby reducing the number of through holes, increasing the density of the circuit, and increasing the reliability of the electrical connection between the interlayer circuit conductor layers. Furthermore, since prepreg insulation notes are not used in the interlayer insulation layer, the thickness can be reduced.

実施例 以下、本発明の一実施例を図面を参照しながら説明する
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図A−Bは本発明の第一の実施例に於ける6層の多
層プリント配線板の製造法を説明するための主要製造工
程の断面図である。
FIGS. 1A-B are cross-sectional views of the main manufacturing steps for explaining the method of manufacturing a six-layer multilayer printed wiring board in the first embodiment of the present invention.

第1図に於いて、7は絶縁基板、8は絶縁基板に設けた
貫通孔、9a、9bは第−耐めっき性レジスト層、10
a、10bは無電解銅めっきで形成した第一の内層回路
導体層、11.a、11bは絶縁樹脂層による層間絶縁
膜、12a、12bは第二の耐めっき性レジスト層、1
3a、13bは第二の内層回路導体層、14a、14b
は接着剤層、15a、15bは金属銅箔、16は貫通孔
、17は銅めっき金属層、18a、18bは最外層回路
導体層である。
In FIG. 1, 7 is an insulating substrate, 8 is a through hole provided in the insulating substrate, 9a and 9b are plating-resistant resist layers, 10
a, 10b are first inner circuit conductor layers formed by electroless copper plating; 11. a and 11b are interlayer insulating films made of insulating resin layers; 12a and 12b are second plating-resistant resist layers;
3a, 13b are second inner circuit conductor layers, 14a, 14b
15a and 15b are adhesive layers, 15a and 15b are metal copper foils, 16 is a through hole, 17 is a copper-plated metal layer, and 18a and 18b are outermost circuit conductor layers.

以上の構成から成る6層の多層プリント配線板について
以下その製造方法の詳細な実施例を説明する。
A detailed example of a manufacturing method for the six-layer multilayer printed wiring board having the above structure will be described below.

本実施例では先ず第1図Aに示すようにガラスエポキン
積層板や紙フエノール積層板、ガラスポリイミド積層板
等の合成樹脂系の絶縁基板7の必要な箇所に貫通孔8を
あけ、この絶縁基板7に接着剤を塗布するかまたは化学
的、物理的、機械的方法によってその表面を粗面化し、
これを塩化第ススと塩化パラジウムの塩酸性溶液に順次
浸漬してその表裏両面に金属バランラムの微粒子核から
なる触媒層を付着させ、−旦乾燥する。その後この絶縁
基板の表裏両面層にスクリーン印刷法かフォト法によっ
て逆配線図形状に第−酎めっき性レジスト層9a、9b
を被覆し、この基板を銅錯塩のアルカリ溶液とホルマリ
ンから成るpH12〜13の無電解銅めっき液に浸漬し
て触媒層か露出した絶縁基板7の表裏面と貫通孔8の内
壁面とに金属銅を析出させて、貫通孔8を導通化した第
の内層回路導体層10a、10bを形成する。
In this embodiment, first, as shown in FIG. 1A, through-holes 8 are made at necessary locations in an insulating substrate 7 made of synthetic resin such as a glass epoxy laminate, a paper phenol laminate, or a glass polyimide laminate. by applying adhesive to or roughening its surface by chemical, physical or mechanical methods,
This is sequentially immersed in a hydrochloric acid solution of stannous chloride and palladium chloride to deposit a catalyst layer consisting of fine particle cores of metal balanrum on both the front and back surfaces, and then dried. Thereafter, the first and second plating resist layers 9a and 9b are formed into a reverse wiring diagram shape on both the front and back layers of this insulating substrate by screen printing or photo method.
The substrate is immersed in an electroless copper plating solution of pH 12 to 13 consisting of an alkaline solution of a copper complex salt and formalin to coat the catalyst layer or the exposed front and back surfaces of the insulating substrate 7 and the inner wall surface of the through hole 8 with metal. Copper is deposited to form the second inner circuit conductor layers 10a and 10b in which the through holes 8 are made conductive.

この場合、めっき性レジスト層9a、9bとしては無電
解銅めっき後に除去してもしなくてもよいが、本実施例
では内層回路導体層10a、10bの平滑化をはかるた
めに除去しないタイプの耐めっきレジスト使用した。
In this case, the plating resist layers 9a and 9b may or may not be removed after electroless copper plating, but in this example, the resist layers 9a and 9b are not removed in order to smooth the inner circuit conductor layers 10a and 10b. Plating resist was used.

そして、そのレジスト材料としては耐アルカリ性を具備
する必要があるためにエポキシ系の樹脂を使用し、この
樹脂にアルミナやンリヵ、炭酸力ルンウム等の無機質の
充填剤を混練したペーストを作り、スクリーン印刷法に
よって絶縁基板7の表裏両面に逆配線図形状に被覆した
Since the resist material needs to have alkali resistance, an epoxy resin is used, and a paste is made by kneading this resin with inorganic fillers such as alumina, phosphorus, carbonate, etc., and screen printing is performed. Both the front and back surfaces of the insulating substrate 7 were coated in the shape of a reverse wiring diagram using a method.

次いで、この第一の内層回路導体層10a、10bの表
面にその一部か露出するようにそれぞれの回路導体面に
絶縁樹脂層11a、llbを選択的に形成するか、その
形成方法としては前述した耐無電解めっき性レンストと
同様にエボキン樹脂にアルミナやンリカ、炭酸カルシウ
ム等の無機質充填剤を混練してペースト状としたものを
スクリーン印刷法によって選択的に塗布し、ブラインド
バイヤーホールを設けるように絶縁樹脂層11a11b
を形成する方法を採る。
Next, insulating resin layers 11a and llb are selectively formed on the respective circuit conductor surfaces of the first inner circuit conductor layers 10a and 10b so that a portion thereof is exposed, or the method for forming them is as described above. Similar to the electroless plating resistant Lenst, Evokin resin is kneaded with inorganic fillers such as alumina, phosphoric acid, and calcium carbonate to form a paste, which is then selectively applied using screen printing to create blind buyer holes. Insulating resin layer 11a11b
Adopt a method to form a

また一方、この絶縁樹脂層11a、llbにブラインド
バイヤーホールを形成する方法として他の実施例として
、アクリル変性した光感光性エポキシ樹脂をフィルム上
に厚くコートし、これを熱ロールを用いて第一の内層回
路導体層10a、10bの表面全体に転写した後、部分
的に紫外線を照射して現像処理を行い、絶縁樹脂層の一
部を取り除いて微細径を有するブラインドバイヤーホー
ルを設けた絶縁樹脂層11a、llbを形成してもよい
On the other hand, as another example of the method of forming blind buyer holes in the insulating resin layers 11a and 11b, a film is thickly coated with an acrylic-modified photosensitive epoxy resin, and this is first coated using a hot roll. After the insulating resin is transferred to the entire surface of the inner circuit conductor layers 10a and 10b, it is partially irradiated with ultraviolet rays and developed, and a part of the insulating resin layer is removed to provide a blind buyer hole with a fine diameter. Layers 11a and llb may also be formed.

それから、この層間絶縁樹脂層11a、llbの表面層
に、その表面を科学的、物理的または機械的方法によっ
て微細に粗面化し、活性化処理を行って無電解めっきの
触媒核を全面に付着する。
Then, the surfaces of the interlayer insulating resin layers 11a and llb are finely roughened by a scientific, physical or mechanical method, and activated to adhere catalyst nuclei for electroless plating to the entire surface. do.

そしてスクリーン印刷法によって第二耐めっきレンズ)
12a、12bを逆配線図形状に塗布して硬化させた後
で、無電解銅めっきを行い、絶縁樹脂層11a、llb
に設けた微細孔(ブラインドバイヤーホール)を通して
第一の内層回路導体層10a、10bと電気的に接続さ
れた第二の内層回路導体層13a、13bを形成し、4
層の回路導体層を多層化した内層配線基板を得る。
and second plating-resistant lens by screen printing method)
After coating 12a and 12b in a reverse wiring diagram shape and curing, electroless copper plating is performed to form insulating resin layers 11a and llb.
forming second inner circuit conductor layers 13a, 13b electrically connected to the first inner circuit conductor layers 10a, 10b through micro holes (blind buyer holes) provided in 4;
An inner layer wiring board having multiple circuit conductor layers is obtained.

ソシて、第1図Bに示すようにこの4層の内層配線基板
の表裏両面それぞれに、接着剤14a14bを一方の面
に塗布した金属銅箔15a15bを重ねて熱プレスによ
り加圧、加熱して一体成形を行った後で、必要な箇所に
貫通孔]6をあけ、無電銅解めっきと電解銅めっきを併
用して、貫通孔16の内壁面と金属銅箔15a、15b
の表裏両面に銅めっき金属層17を析出する。
Then, as shown in FIG. 1B, metallic copper foils 15a15b coated with adhesive 14a14b on one side are stacked on both the front and back surfaces of the four-layer inner layer wiring board, and pressed and heated using a hot press. After performing the integral molding, through-holes] 6 are drilled at necessary locations, and the inner wall surface of the through-hole 16 and the metal copper foils 15a, 15b are coated using a combination of electroless copper plating and electrolytic copper plating.
Copper-plated metal layers 17 are deposited on both the front and back surfaces.

この場合、金属銅箔15a、15bの片面に塗布した接
着剤層14a、14bは金属銅箔との接着性に優れてい
ることはもとより、絶縁特性、耐熱性等の特性にも優れ
ていることか必要であり、本実施例ではこれらの諸特性
を満足する接着剤として、エポキシ系の樹脂を使用した
In this case, the adhesive layers 14a and 14b applied to one side of the metal copper foils 15a and 15b not only have excellent adhesion to the metal copper foils, but also have excellent properties such as insulation properties and heat resistance. In this example, an epoxy resin was used as an adhesive that satisfies these characteristics.

また一方、他の実施例では、この接着剤14a、14b
にプリプレグ絶縁ンートを使用して金属銅箔15a、1
5bを内層配線基板の表裏面に接着した。
On the other hand, in other embodiments, the adhesives 14a, 14b
Metallic copper foil 15a, 1 using prepreg insulation
5b was adhered to the front and back surfaces of the inner layer wiring board.

これにより層間絶縁特性と耐熱、接着性に優れた多層プ
リント配線板を作ることができた。
As a result, we were able to create a multilayer printed wiring board with excellent interlayer insulation properties, heat resistance, and adhesive properties.

それから第1図Cに示すように、フォトエツチング法等
の公知の方法によって最外層の不要な銅めっき金属層を
溶解除去して、必要とする最外層回路導体層18a、1
8bを形成し、6層の多層プリント配線板を完成させた
Then, as shown in FIG. 1C, the unnecessary outermost copper-plated metal layer is dissolved and removed by a known method such as photoetching, and the necessary outermost circuit conductor layers 18a, 1 are removed.
8b was formed to complete a six-layer multilayer printed wiring board.

この方法により作られた多層プリント配線板は最外層回
路導体層18a、18bか金属銅箔15a15bを接着
剤14a、14bによって内層配線基板に強面に接着し
た後で、エツチング法によって回路形成したものである
ので、回路導体層の信頼性が十分確保されるものである
The multilayer printed wiring board made by this method is one in which the outermost circuit conductor layers 18a, 18b or the metal copper foils 15a, 15b are strongly bonded to the inner layer wiring board with adhesives 14a, 14b, and then circuits are formed by etching. Therefore, the reliability of the circuit conductor layer is sufficiently ensured.

以上の説明から明らかなように、本実施例による多層プ
リント配線板は絶縁基板の表裏両面に無電解銅めっき法
による回路導体層と絶縁樹脂層による絶縁層を交互に形
成して任意の層数に多層化し、層間の回路導体層を絶縁
基板に設けた貫通孔と絶縁樹脂層に設けた貫通しない微
細孔を通して電気的に接続した内層配線基板を構成し、
この内層配線基板の最外層に接着剤層を介して金属銅箔
を接着してからフォトエツチング法によって回路導体層
を形成した多層配線板である。
As is clear from the above description, the multilayer printed wiring board according to the present example has circuit conductor layers formed by electroless copper plating and insulating layers formed by insulating resin layers alternately formed on both the front and back sides of an insulating substrate. constitute an inner layer wiring board in which the circuit conductor layers between the layers are electrically connected through through holes provided in the insulating substrate and non-penetrating micro holes provided in the insulating resin layer,
This is a multilayer wiring board in which a metal copper foil is bonded to the outermost layer of this inner wiring board via an adhesive layer, and then a circuit conductor layer is formed by photoetching.

従って、本発明による多層プリント配線板は内層の回路
導体層相互が貫通孔だけでなく、絶縁樹脂層に設けた微
細孔によって接続された構成となるために貫通孔の数が
大幅に削減されると共に、この接続形態ではスミア−に
よる接続不良か皆無となり回路導体層の層間接続の信頼
性か改善されるという効果の他に、内層の層間絶縁層に
分厚ξプリプレグシートを使用しないために多層プリン
ト配線板の薄型化かはかれるという従来例にない効果か
得られるものである。
Therefore, in the multilayer printed wiring board according to the present invention, the inner circuit conductor layers are connected not only by through holes but also by micro holes provided in the insulating resin layer, so the number of through holes is significantly reduced. At the same time, this connection type has the effect of eliminating connection failures due to smearing and improving the reliability of interlayer connections between circuit conductor layers. In addition, since a thick ξ prepreg sheet is not used for the inner interlayer insulating layer, multilayer printing is possible. This provides an unprecedented effect of making the wiring board thinner and thinner.

発明の効果 以上のように本発明によれば、内層回路導体層相互か貫
通孔のみによる接続形態をとることかなくなるので、貫
通孔の孔数か減少して回路の高密度化かはかれると共に
層間回路導体層間の電気的接続の信頼性か向上し、さら
には層間絶縁層にフリプレグ絶縁シートを使用しないた
め薄型化か実現されることとなる。
Effects of the Invention As described above, according to the present invention, it is no longer necessary to connect the inner circuit conductor layers to each other or only through the through holes, thereby reducing the number of through holes and increasing the density of the circuit. The reliability of the electrical connection between the circuit conductor layers is improved, and furthermore, since no Flipreg insulating sheet is used for the interlayer insulating layer, the thickness can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A−Cは本発明の一実施例に於ける多層プリント
配線板の製造工程を示す断面図、第2図A−Bは従来例
による多層プリント配線板の製造工程を説明する断面図
である。 7・・・・・・絶縁基板、8・・・・・・絶縁基板に設
けた貫通孔、9a、9b・・・・・・第−耐めっきレジ
スト、10a10b・・・・・・第一内層回路導体層、
lla、llb・・・・・・絶縁樹脂層、12a、12
b・・・・・・第三組めっきレジスト、13a、13b
・・・・・・第二内層回路導体層、14 a、  14
 b・・−−−−接着剤層、15a、15b・・・・・
・金属銅箔、16・・・・・・貫通孔、17・・・・・
・銅めっき金属層、18a、18b・・・・・・最外層
回路導体層。 代理人の氏名 弁理士 小蝦治明 ほか2名IO /
FIGS. 1A-C are cross-sectional views illustrating the manufacturing process of a multilayer printed wiring board according to an embodiment of the present invention, and FIGS. 2A-B are sectional views illustrating the manufacturing process of a multilayer printed wiring board according to a conventional example. It is. 7...Insulating substrate, 8...Through hole provided in the insulating substrate, 9a, 9b...-th plating resistant resist, 10a10b...first inner layer circuit conductor layer,
lla, llb...Insulating resin layer, 12a, 12
b... Third set of plating resists, 13a, 13b
...Second inner circuit conductor layer, 14 a, 14
b...---Adhesive layer, 15a, 15b...
・Metal copper foil, 16...Through hole, 17...
- Copper plated metal layer, 18a, 18b... Outermost circuit conductor layer. Name of agent: Patent attorney Haruaki Koebi and 2 others IO /

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁基板の表裏両面それぞれに回路導体層と絶縁
樹脂層を交互に形成しかつ前記絶縁基板の貫通孔及び絶
縁樹脂層に設けたブラインドバイヤホールを通して回路
導体層相互が電気的に接続するように任意の層数の内層
配線基板を構成し、前記内層配線基板の表裏両面層に接
着剤層を介して金属銅はくを接着し、その後にフォトエ
ッチング法によって前記内層回路導体層と電気的に接続
される最外層の回路導体層を形成する多層プリント配線
板の製造方法。
(1) A circuit conductor layer and an insulating resin layer are alternately formed on each of the front and back surfaces of an insulating substrate, and the circuit conductor layers are electrically connected to each other through a through hole in the insulating substrate and a blind via hole provided in the insulating resin layer. An inner layer wiring board with an arbitrary number of layers is constructed as shown in FIG. A method for manufacturing a multilayer printed wiring board, which forms an outermost circuit conductor layer that is connected to the outermost circuit conductor layer.
(2)接着剤層としてプリプレグ絶縁シートを用いた請
求項1記載の多層プリント配線板の製造方法。
(2) The method for manufacturing a multilayer printed wiring board according to claim 1, wherein a prepreg insulating sheet is used as the adhesive layer.
JP2231739A 1990-08-31 1990-08-31 Manufacture of multilayer printed wiring board Pending JPH04112596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2231739A JPH04112596A (en) 1990-08-31 1990-08-31 Manufacture of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2231739A JPH04112596A (en) 1990-08-31 1990-08-31 Manufacture of multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH04112596A true JPH04112596A (en) 1992-04-14

Family

ID=16928283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2231739A Pending JPH04112596A (en) 1990-08-31 1990-08-31 Manufacture of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH04112596A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09232759A (en) * 1996-02-28 1997-09-05 Hitachi Aic Inc Multilayered printed-wiring board and manufacture of multilayered printed-wiring board
US6376053B1 (en) * 1996-12-26 2002-04-23 Ajinomoto Co., Inc. Inter-laminar adhesive film for multi-layer printed wiring board and multi-layer printed wiring board using the same
JP2007059803A (en) * 2005-08-26 2007-03-08 Fuji Xerox Co Ltd Printed circuit board, electronic substrate, and electronic apparatus
US7278205B2 (en) * 2002-08-19 2007-10-09 Taiyo Yuden Co., Ltd. Multilayer printed wiring board and production method therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09232759A (en) * 1996-02-28 1997-09-05 Hitachi Aic Inc Multilayered printed-wiring board and manufacture of multilayered printed-wiring board
US6376053B1 (en) * 1996-12-26 2002-04-23 Ajinomoto Co., Inc. Inter-laminar adhesive film for multi-layer printed wiring board and multi-layer printed wiring board using the same
US6881293B2 (en) 1996-12-26 2005-04-19 Ajinomoto Co., Inc. Process for producing a multi-layer printer wiring board
US7278205B2 (en) * 2002-08-19 2007-10-09 Taiyo Yuden Co., Ltd. Multilayer printed wiring board and production method therefor
JP2007059803A (en) * 2005-08-26 2007-03-08 Fuji Xerox Co Ltd Printed circuit board, electronic substrate, and electronic apparatus

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