JPH04120590A - LCD drive device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal drive device for driving a liquid crystal display panel used in, for example, a liquid crystal television receiver.

[Prior Art] It is known that when driving a liquid crystal display panel, increasing the driving frame frequency improves contrast.

Fig. 4 shows a conventional liquid crystal drive device in which the frame frequency of the drive is increased in order to improve display contrast, and Fig. 5 shows the timing diagram of the operating state of the liquid crystal drive device shown in Fig. 4. It is a chart.

First, the receiving circuit 1 extracts the video signal Sv, the horizontal synchronizing signal φH1 and the vertical synchronizing signal φV from the received television signal, and the video signal Sv is sent to the A/D converter 3, the horizontal synchronizing signal φH and the vertical synchronizing signal φ■ are sent to the control circuit 2, respectively. The control circuit 2 generates a start signal ST, a clock signal φS,
Generates various timing signals such as latch signal φn1 inverted signal φF1 switching signal SEL, address designation signals ADI, AD2, read/write signal R/W, shift registers 5, 8, 9, drive circuits 6, 10° 11, switching circuit 4
, memories A, B, etc., and also generates a plurality of types of liquid crystal drive voltages VLC9 and outputs them to drive circuits 6, 10, 1.1.

On the other hand, the A/D converter 3 converts the input video signal Sv into 1-bit digital video data E and outputs it to the memories A and B. The memory AB receives the address designation signal AD1 from the control circuit 2. ．． ．． Using AD2 and the read/write signal R/W, memory A stores the even fields (nn+2, n+4, ...) of video data E, and memory B stores the odd fields (n+1, n+3, ...). loads.

Next, the video data of n fields read into memory A is field n+1, which is twice the writing speed.
That is, the video data of the n+1 field read into the memory B is read out twice at twice the speed of normal video data and outputted to the switching circuit 4 as the output signal EA. The data is read twice at twice the writing speed, that is, twice the speed of normal video data, and is output to the switching circuit 4 as a pressure signal EB. The output signals EA and EB manually input to the switching circuit 4 are the switching signal SEL from the control circuit 2.
The data is switched every one field time, outputted to the shift register 5 as data DAB, and stored in the shift register 5 in synchronization with the clock signal φS of the control circuit 2. The data DAB stored in the shift register 5 is latched every 1/2H (horizontal scanning period) by the latch signal φn from the control circuit 2 in the segment drive circuit 6, and is AC driven by the inverted signal φF. The level is shifted to the liquid crystal drive voltage VLC whose polarity is inverted to drive the segment electrodes of the liquid crystal display panel 7.

Furthermore, as shown in FIG. 5, on the common side of the liquid crystal display panel 7, a 1H (horizontal scanning period) start signal ST from the control circuit 2 is input to the shift register 8. The shift register 8 is sequentially shifted in each horizontal scanning period).
, 9 from each pressure signal X' 1 to X' L20 ,
X'121 to X'240 each correspond to drive two common electrodes, and the common electrode drive circuit 10
．． 1.1 d is added. This common electrode drive circuit] 0°11 is each output signal X'1 to X'120. X' 1
21 -
The signal is level-shifted to C and applied to the common electrodes of the liquid crystal display panel 7, and the common electrodes are driven two at a time.

[Problems to be Solved by the Invention] As described above, the time for one selection of the common electrode of the liquid crystal display panel is halved, the selection frequency is doubled, and the contrast is improved. However, in this conventional liquid crystal driving device, the transfer speed of the shift register must be doubled, and the memory capacity is required for 2 fields x bits, both of which lead to an increase in cost.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and it is possible to reduce the amount of memory used as much as possible, and to increase the frame frequency of liquid crystal drive without increasing the data transfer speed to the segment electrode drive circuit. The purpose is to provide a liquid crystal driving device.

[Means and effects for solving the problems] In order to solve the above problems, the present invention provides data output means for dividing a video image into a plurality of parts and sequentially outputting them at staggered times, and video data from this data output means. supply means for time-divisionally supplying video data to the segment drive means during at least 1H period, and common drive means for selecting a plurality of commons during at least 1H in response to time-division of the video data supplied from the supply means. For example, the storage data output means stores the upper 3 bits of the video data, and outputs the upper 3 bits of video data into 1 bit for each 1/4 field. It is output as video data with a delay of 1/4 field. The video data supply means combines the stored data from the stored data output means and the video data not passed through the storage means during a 1H period, and outputs the synthesized data to the segment electrode driving means. The segment electrodes are driven in accordance with the video data output from the video data supply means. Further, the common electrode drive means drives a plurality of common electrodes each corresponding to each video data outputted from the video data supply means during the 1H period.

〔Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a liquid crystal driving device according to an embodiment of the present invention, and FIG.
The figure is a timing chart showing the operating state and data contents of the liquid crystal driving device shown in FIG.

First, the receiving circuit 1 extracts the video signal Sv, the horizontal synchronizing signal φH, and the vertical synchronizing signal φV from the received television signal, and the video signal Sv is sent to the A/D converter 3, where it is sent to the A/D converter 3, where it is converted into the horizontal synchronizing signal φH and the vertical synchronizing signal φV. are sent to the control circuit 12, respectively. The control circuit 12 generates a start signal STo, a clock signal ψs1, a latch signal φn1, an inverted signal φF, and an output prohibition signal I from the input horizontal synchronization signal φH and vertical synchronization signal φV.
NHI, INH21NH31NH4, address designation signals ADI, AD2. AD3, read/write signal R/W
l, R/W2. Generates various timing signals such as R/W3, shifts register 15, 18, drive circuits i6, 20,
21, 22° 23, memory Ml, M2. In addition to outputting to M3, output control circuits 24.25, 26.27, etc., a drive circuit 1620.2 generates multiple types of liquid crystal drive voltages VLC.
Output on 1.22.23.

On the other hand, the A/D converter 3 converts the input video signal Sv into video data E of 4 bits (D+ to D4), for example, and inputs the data to each memory Ml.

M2. M3, each memory Ml, M2 . M3 is the corresponding addressing signal A from the control circuit 12;
D1. AD2. AD3 and read/write signal R/
Wl, R/W2. According to R/W3, the upper 3 bits of the video data E are read in correspondence with each other. That is,
Memory M1 has a capacity of 1/4 field x 1 bit, memory M2 has a capacity of 1/2 field x 1 bit, memory M3 has a capacity of 3/4 field x 1 bit, and memory M1 has a capacity of 1/2 field x 1 bit. Data for 4 fields x 1 bit is read, data for 1/2 field x 1 bit is read into memory M2, and data for 1/2 field x 1 bit is read into memory M3.
Data for 3/4 field x 1 bit is read into.

Next, the 1/4 field read into memory M1 ×
After 1/4 field, 1 bit of data is read out according to the addressing signal ADI and read/write signal R/Wl from the control circuit 12, and 1 bit (
The data for 1/2 field x 1 bit which is output to the shift register 15 as data Db of D4) and read into the memory M2 is sent to the control circuit 12 after 1/2 field.
According to the address designation signal AD2 and the read/write signal R/W2 from
) is output to the shift register 15 as data Dc,
The data of 3/4 field x 1 bit read into memory M3 is read out after 3/4 field according to address designation signal AD3 and read/write signal R/W3 from control circuit 12, and becomes 1 bit. (D2) is output to the shift register 15 as data Dd. The video data Da of the least significant bit (Dl) without going through the memory from the A/D converter 3 input to the shift register 15 and the data Db-Dd of the upper three bits (D4-D2) from the memories M1-M3 are as follows. Clock signal φS of control circuit 12
The data is stored in the 4-bit shift register 15 in synchronization with . Data D a stored in this shift register 15
-D d is simultaneously output to the segment drive circuit 16 in the next horizontal scanning period H. And this data Da~Dd
is latched every 1H (horizontal scanning period) by the latch signal φn from the control circuit 12 in the segment drive circuit 16, and is level-shifted to a liquid crystal drive voltage VLC whose polarity is inverted to perform AC driving by the inversion signal φF. The segment electrodes of the liquid crystal display panel 7 are driven.

This segment drive circuit 16 has 16 gray levels (0, 1, 2...
15), the segment electrodes are driven in each gradation from 4-bit video data], and the drive timing at 1H in 2.4.8 is preset as shown in Figure 3, so the four common By making it correspond to the selection timing of the electrodes, video data can be displayed on each pixel (the intersection of the segment electrode and the common electrode) for each bit of the 4-bit video data.

That is, as shown in FIG. 2, the common side of the liquid crystal display panel 7 receives a 1H (horizontal scanning period) start signal S corresponding to the video data of each part and component from the control circuit 12.
T, is input to the shift register 18 and the clock signal φn
is sequentially shifted in the shift register every 1H (horizontal scanning period).

Therefore, each output signal from the shift register 18 is always transmitted to the output control circuits 24, 22, 23 so that the common electrode drive circuits 20, 21, 22, 23 respectively drive the common electrodes.
5, 26, and 27, but the output control circuits 24, 25
．． 26.27 are output inhibit signals INHI, INH2, lNH3, lN whose selection is prohibited when the level is NO1.
According to H4, shift 1/star 18 force) et al.'s ■force f word X'l~X' 81),
0, X'121~X 1.80X'181~X
Common electrode drive circuit 20 corresponding to '240,
Add to 21, 22, and 23. This common electrode drive circuit'
>0. 21, 22, and 23 are each output signal X"1 to X'
60. X'61-X120X'121-X' 1
80, corresponding to X'181 to X'240, the level of the liquid crystal display panel 7 is shifted to the liquid crystal drive voltage VLC whose polarity is inverted so as to perform AC driving by the inverted signal φF.
is applied to the common electrode to drive the common electrode.

As described above, in the segment I electrode of the liquid crystal display panel 7, (1H, 61H, 121H, 181H) (2H, 62
H, 122H, 182H), (3H63H, 123H,
183H), (4H, 64B.

124H, 184H)・・・・・・・・・・・・・・・
When inputting data, at the common electrode (Xi, X6
1. X121X181), (X2, X6
2. X122, X1g2) (X3, X
83. X123, X183), (X4
, X64°X124, X184)...
...... is selected and the correct drive is performed.

[Effects of the Invention] As described above, according to the present invention, there is provided a data output means for dividing video data into a plurality of parts and sequentially outputting the video data at staggered times;
supply means for time-divisionally synthesizing and supplying the synthesized data to the segment drive means during the H period; and a common drive for selecting a plurality of commons during at least 1H corresponding to the time-division of the video data supplied from the supply means. Therefore, it is possible to drive the liquid crystal without increasing the data transfer speed of the segment electrode drive circuit and without increasing the transfer speed of the common electrode drive circuit, using a memory with a smaller capacity than conventional ones. It is possible to provide a liquid crystal driving device that quadruples the frame frequency of .

[Brief explanation of drawings]

Figures 1 to 3 show one embodiment of the present invention.
The figure is a block diagram showing the circuit configuration of the liquid crystal drive device, FIG. 2 is an explanatory diagram showing the waveforms and data contents of each part of FIG. 1,
FIG. 3 is a diagram showing an example of the gradation waveform of the segment drive circuit,
FIG. 4 is a configuration explanatory diagram showing an example of a conventional liquid crystal driving device;
FIG. 5 is an explanatory diagram showing waveforms and data contents of each part in FIG. 4. M1 to M3...memory, l-...receiving circuit, 3...
A/D converter, 7... Liquid crystal display panel, 12... Control circuit, 1518... Shift register, 16... Segment drive circuit, 20-23... Common electrode drive circuit, 24-27 ...Output control circuit.

Claims (1)

[Scope of Claims] Data output means for dividing video data into a plurality of parts and sequentially outputting them at staggered times; and video data sequentially outputted from the data output means to segment driving means in a time division manner during at least 1H period. A liquid crystal driving device comprising: a supply means for supplying video data; and a common drive means for selecting a plurality of commons during at least 1H in accordance with time division of the video data supplied by the supply means.