JPH0444092A - Liquid crystal display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display device for driving a liquid crystal used in, for example, a liquid crystal television receiver.

[Prior Art] It is known that when driving a liquid crystal, increasing the driving frame frequency improves the contrast.

Fig. 5 shows a conventional liquid crystal drive device in which the frame frequency of the drive is increased to improve display contrast, and Fig. 6 shows the timing diagram of the operating state of the liquid crystal drive device in Fig. 5. It is a chart.

First, the receiving circuit extracts the video signal Sv, horizontal synchronizing signal φH, and vertical synchronizing signal φV from the received television signal.The video signal Sv is sent to the A/D converter 3, and the horizontal synchronizing signal φH and vertical synchronizing signal The signals are sent to the control circuit 2, respectively. The control circuit 2 generates a start signal ST and a tarlock signal φs5 from the input horizontal synchronizing signal φH and vertical synchronizing signal φV.
Generates various timing signals such as latch signal φn1 inverted signal φF1 switching signal SEL, address designation signals ADI, AD2, read/write signal R/W, shift registers 5, 8, 9, drive circuits 6, 10° 11, switching circuit 4
, memories A, B, etc., and also generates a plurality of types of liquid crystal drive voltages VLC and outputs them to drive circuits 6, 10, and 11.

On the other hand, the A/D converter 3 converts the input video signal Sv into 1-bit digital video data E and outputs it to the memories A and B. The memories A and B are connected to the control circuit 2.
Memory A stores the even fields (n, n+2.n+4...) of the video data E by the addressing signals ADD, AD2 and the read/write signal R/W from the memory A, and the odd fields (n+1+n''3+...) from the memory A. ...)
is read by memory B.

Next, the video data of n fields read into memory A is field n+1, which is twice the writing speed.
That is, the video data of the n+1 field read into the memory B is read out twice at twice the speed of normal video data and outputted to the switching circuit 4 as the output signal EA. The data is read twice at twice the writing speed, that is, twice the speed of normal video data, and is output to the switching circuit 4 as an output signal EB. The output signals EA and EB input to the switching circuit 4 are the switching signal SEL from the control circuit 2.
The data is switched every one field time, outputted to the shift register 5 as data DAB, and stored in the shift register 5 in synchronization with the clock signal φS of the control circuit 2. The data DAB stored in the shift register 5 is latched every 1/2H (horizontal scanning period) by the latch signal φn from the control circuit 2 in the segment drive circuit 6, and is AC driven by the inverted signal φF. The level is shifted to the liquid crystal drive voltage VLC whose polarity is inverted to drive the segment electrodes of the liquid crystal display panel 7.

Further, on the common side of the liquid crystal display panel 7, an IH (horizontal scanning period) start signal ST from the control circuit 2 is input to shift registers 8 and 9, and a clock signal
Since they are sequentially shifted in the shift register every /2H (horizontal scanning period), each output signal X'1 to X'120, X'121 to X'2 from the shift register 8.9
40 are added to corresponding common electrode drive circuits 10 and 11 to drive two common electrodes, respectively. This common electrode drive circuit 10.11 outputs each output signal X'l
-X' 120, X' 121 - is 2
Driven by books.

[Problems to be Solved by the Invention] As described above, the time for one selection of the common electrode of the liquid crystal display panel is halved, the selection frequency is doubled, and recontrast is improved. However, in this conventional liquid crystal driving device, the transfer speed of the shift register must be doubled and the memory capacity must be equivalent to two fields, both of which lead to an increase in cost.

Therefore, the present invention has been made in view of the above circumstances, so that it is possible to reduce the amount of memory used as much as possible, and to increase the frame frequency of liquid crystal drive without increasing the data transfer speed to the segment electrode drive circuit. Moreover, it is an object of the present invention to provide a liquid crystal display device that can display correct gradation.

[Means and effects for solving the problem] A storage means for storing at least the most significant bit of video data of a series of video data, and a plurality of upper bits of the video data that are not passed through this storage means are rearranged in a predetermined order. an adding means for adding the least significant bit to the data added;
A switching means for alternately outputting data during each horizontal scanning period, a segment electrode driving means for driving segment electrodes according to data from the switching means, and a plurality of common electrodes corresponding to video data output from the switching means. It is equipped with a common electrode drive means that drives each
The most significant bit of video data stored in a memory with a capacity equal to the number of fields x 1 bit, and the top 3 bits of raw video data that does not go through memory, are rearranged to display correct gradation. The segment electrodes are driven by alternately outputting the video data obtained by adding the lowest bit bits every horizontal scanning period, and the common electrodes corresponding to the video data are driven two at a time. .

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a liquid crystal driving device according to an embodiment of the present invention, and FIG.
The figure is a timing chart showing the operating state and data contents of the liquid crystal driving device shown in FIG.

First, in the receiving circuit 1, the video signal Sv, the horizontal synchronizing signal φH, and the vertical synchronizing signal φV are extracted from the received television signal, and the video signal Sv is sent to the A/D converter 3. The signals are sent to the control circuit 12, respectively. The control circuit 12 generates a start signal STo, a clock signal φs1, a latch signal φ0, an inverted signal φF, and an output inhibit signal I from the input horizontal synchronizing signal φH and vertical synchronizing signal φV.
NHI, 2, switching signal 5EI7, address designation signal A
D, generates various timing signals such as read/write signal R/W, shift register 1518.19, drive circuits 16, 20, 21, addition/switching circuit 14, memory M,
In addition to outputting to the output control circuits 22, 23, etc., multiple types of liquid crystal drive voltages VLC are generated and the drive circuits 16, 20, 21
Output to.

On the other hand, the A/D converter 3 converts the input video signal Sv into bits, for example, as shown in FIG.
B, D2, D+, Do) video pig E. At the same time, the memory M outputs data Eo-MSB of the most significant bit D3 of the image data E according to the address designation signal AD and the read/write signal R/W from the control circuit 2. Load.

At this time, the data for 1/2 field read into the memory M is read every LH (41 scanning periods) after /2 field according to the address designation signal AD and the read/write signal R/W from the control circuit 2. is read out,
The 3 bits consisting of the most binary bits as shown in Figure 4 (
DB from the top.

DB, DB=b) is outputted to the addition/switching circuit]4 as video data EB.

Also, 4-bit video data E (from the higher order, D2.DDo) as shown in FIG. 4 is converted by the A/D converter 3. is output from the addition/switching circuit 14. Addition/switching circuit] 4 is an AND circuit 31 to 3 as shown in FIG.
6. OR circuits 37-39. The switching circuit 4 includes an inverter 40 and an adder 30. The adder 30 receives video data E. (DB, D2.D, from the top.

Data EA' of 3 bits (D2.D, DB = a from the higher order) and the lowest Pi I-D o is input and added (a + D.-a r
) and added video data EA ((D2, D+, D
B) Ten ri. ) to the switching circuit 41.

Addition video data EA ((D2,
I) + , DB )→-Do) and the most significant bit video pig EB ( DB , DB , DB ) from memory M
) is outputted alternately every IH (horizontal scanning period) by this switching circuit 4 according to the switching signal SEL from the control circuit 2, and is inputted to the shift register 15 as a pig DAB. This data DAB is stored in the shift register 5 in synchronization with the clock signal φS of the control circuit 2. Data DAB stored in this shift register 15
is latched in each IH (horizontal scanning period) by the latch signal φn from the control circuit]2 in the segment drive circuit 16, and level-shifted to a liquid crystal drive voltage VLC whose polarity is inverted to perform AC drive by the inversion signal φF. The segment electrodes of the liquid crystal display panel 7 are driven.

Furthermore, the common side of the liquid crystal display panel 7 is connected to a control circuit 12.
A start signal ST for 2H (horizontal scanning period) from 2H (horizontal scanning period) is input to the shift register 18.19, and is sequentially shifted in the shift register every IH (horizontal scanning period) by clock signal φn. Therefore, each output signal from the shift register 18.19 is always output to the output control circuit 22.23 so that the common electrode drive circuit 20.21 drives two common electrodes each. ．．
23 is an output inhibit signal INHI which is inverted every IH (horizontal scanning period) in synchronization with the horizontal synchronizing signal φH, and I according to 2.
Shift register 18.H (horizontal scanning period) alternately.
Output signals from 19 X' 1 to X' 120 , X'
121 to X'240 are respectively added to the corresponding common electrode drive circuits 20 and 21. This common electrode drive circuit 2
0.21 is for each output signal X' 1 to X' 120 , X
' 121 - do.

That is, the added video data EA ((D2, D+, D3)+Do as shown in FIG. 4 is displayed on the liquid crystal display panel 7.
-a') and the video data EB of the most significant bit.
By alternately displaying (D3, D3, D3 = b), the display gradation becomes a correct gradation proportional to a'.

FIG. 3 shows an example of the addition/switching circuit 14, which includes an adder 30, AND circuits 31 to 36 . OR circuits 37-39.
It is composed of a switching circuit 41 made up of an inverter 40.

That is, video data E as shown in FIG. (D3 (
MS B), D2, I)+.

DO(LSB)) is input to the input terminal A3°A2. A
I, added to Bl. In this case, the upper 3 bits of the video data Eo (03.D2, I)+, Do from the higher order are rearranged to create 3-bit data (D2.D+, D3-a from the upper order) as shown in FIG. It is connected so that EA' is input. As a result, the output terminal Σ of the adder 30
3. Σ2. In Σ1, the upper 3 bits of the video data Eo (from the upper order, D2°D, Do) are rearranged.
3 bits (D2.D, from higher order) as shown in FIG.

D3-a) data EA and the least significant bit D.

Addition video data EA obtained by adding (a + a′)
((D2, D+, D3)+DO=a') is obtained. This added video data EA ((D2, D+
.

D3) +D. =a') is applied to one input terminal of AND circuits 31-33, and data Ea (most significant bit D3) is applied to one input terminal of AND circuits 34-36. A switching signal SEL is applied to the other input terminals of the AND circuits 34 to 36, and the AND circuits 31 to 33
The switching signal SEL is connected to the other input terminal of the inverter 40.
added via . The outputs of the AND circuits 31.34 are connected to the input terminals of the OR circuit 37, and the outputs of the AND circuits 32.35
The output of the AND circuit 33 is connected to the input terminal of the OR circuit 38.
．． The outputs of 36 are respectively applied to the input terminals of an OR circuit 39. As a result, the output terminals of the OR circuits 37 to 39 receive D B (M S B ) and p 2 from the higher order.

D, (LSB) data DAB is output and added to the shift register 15.

[Effects of the Invention] As described above, according to the present invention, video data of the most significant bit stored in a memory with a capacity of 1/4 field x 1 number of bits every horizontal scanning period, By rearranging the upper three bits of the raw video data and adding the least significant bit, the video data is output alternately every horizontal scanning period, and the segment electrodes are driven and the video data corresponding to the video data is output. Since the common electrodes are driven two at a time, it is possible to use a memory with a smaller capacity than conventional ones, double the drive frequency without increasing the data transfer speed of the segment electrode drive circuit, and still maintain the correct level. It is possible to provide a liquid crystal display device that can adjust the display.

[Brief explanation of drawings]

Figures 1 to 4 show one embodiment of the present invention.
The figure is a block diagram showing the circuit configuration of the liquid crystal drive device, FIG. 2 is an explanatory diagram showing the waveforms and data contents of each part of FIG. 1,
3 is a circuit configuration diagram showing an example of the addition/switching circuit in FIG. 1, FIG. 4 is an explanatory diagram showing the contents of each data in FIG. 1,
FIG. 5 is a configuration explanatory diagram showing an example of a conventional liquid crystal driving device;
FIG. 6 is an explanatory diagram showing waveforms and data contents of each part in FIG. 5. M...Memory, 1. Receiving circuit, 3. A/D converter, 7
・Liquid crystal display panel, 12... Control circuit, 14... Addition/switching circuit, 15, 1.8.19. Shift register,] 6... Segment drive circuit, 20° 21... Common electrode drive circuit , 2223...output control circuit.

Claims (1)

[Scope of Claims] A storage means for storing at least the most significant bit of video data of a series of video data; and a storage means for storing at least the most significant bit of video data of a series of video data; an addition means for adding bits; and an addition means for alternately outputting the video data added by the addition means and at least the most significant bit video data outputted from the storage means every horizontal scanning period every horizontal scanning period. A switching means, a segment electrode driving means for driving a segment electrode according to data from the switching means, and a common electrode driving means for driving a plurality of common electrodes each corresponding to video data output from the switching means. A liquid crystal display device comprising: