JPH0412559B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to the structure of a horizontally stacked ROM.

(Prior Art) Recently, integrated circuit devices have been rapidly becoming more highly integrated. Along with this, circuits that were conventionally composed only of random logic are now being replaced with programmable circuits in order to reduce the number of elements. For this reason, to store the program
ROMs are also required to be faster and have larger memory capacity. Therefore, due to these requirements, a horizontally stacked ROM, in which transistors are stacked horizontally, is used. This is stacked vertically
This is because ROM has transistors stacked vertically, so the on-resistances of the transistors are connected in series, slowing down the speed, whereas horizontal stacking has transistors connected in parallel, increasing speed. This becomes especially noticeable when the ROM becomes large.

An example of a conventional horizontally stacked ROM of this type is shown in FIG. Here, 1 is a ROM main body, and 2 is a decoding circuit. To explain its operation, first, the input is 2 bits A0 and A1, and the decoded signal is 4 bits D0 to D3.
The final output is 4 bits. The ROM cell has an N-channel horizontally stacked structure, and the N-channel is placed in the part where predetermined information is stored.
It has a structure in which MOS transistors are formed. A precharge signal PG is also input to the ROM, and the ROM is precharged. These timings are shown in FIG. The precharge signal PG has a period T, and in the first half _T1 of the period T, the precharge P channel transistor 4 connected to each output line is turned on to precharge the output signals O0 to O3.
(It becomes "1".) Then, an output appears in the output signals O0 to O3 during the second half _T2 . The input data changes in synchronization with this period T. Therefore, the decoded signals D0 to D3 also change in synchronization with this period T. Among the signals D0 to D3, only the intended signal becomes "1" and all the others become "0". Therefore
If there is a transistor on the target signal line in the ROM, the transistor turns on and changes the output line, which is precharged and set to "1" during the period T1, to "0" during the period T2. Conversely, an output line without a transistor remains precharged and becomes "1". In this way, this ROM
If you want “0”, install a transistor,
If "1" is desired, the desired output can be obtained by designing without providing a transistor.

However, with this configuration, the period of T1 is
The P channel transistor 4 for precharging attached to each output line is turned on, but during this period, the target signal among the decode output signals D0 to D3 becomes "1", so the N Channel transistor 3 is also turned on, and current flows between V _DD and ground. In general, the on-resistance of a transistor is on the order of tens to hundreds [KΩ], so the current flowing at the moment of T1 is several tens [μA] per output, and even several [mA] for 100 outputs. The larger the size, the more noticeable it becomes.
In particular, the P-channel transistor 4 for precharging has a large load capacity and must be precharged during the T1 period, so that gm
Since the current is increased, the current that actually flows becomes significantly larger. Therefore, the power supply wiring must be designed to withstand this current, and the resistance of the power supply wiring inevitably lowers the power supply voltage applied to each transistor 3, 4, causing malfunction. Moreover, the biggest drawback is that it leads to an increase in current consumption. A conventional embodiment improved in this respect is shown in FIG. 3, and its timing is shown in FIG. 4. In this embodiment, an AND circuit 5 is provided at the decode output to prohibit the decode outputs D0 to D3 from becoming "1" during the period T1. As a result, no current flows between V _DD and ground during T1. However, the load capacity of the decode signals D0 to D3 in the ROM is large,
It takes time to change this line from "1" to "0" and from "0" to "1", which reduces the operating speed of the ROM. Therefore, this signal line
Prohibiting the T1 period is undesirable for this speed increase, and is not suitable for recent fast ROMs.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a ROM that has high operating speed and low current consumption.

(Structure of the Invention) The present invention includes a plurality of decoder lines arranged in the row direction, a plurality of output lines arranged in the column direction, and two adjacent output lines in each unit. One source signal line arranged in the column direction between the output lines of the book, first and second power supply lines arranged in the row direction at one end of the plurality of output lines, and the plurality of output lines. a plurality of first field effect transistors of one conductivity type arranged in the row direction on the one end side of the line and connected between one end of the output line to which the source-drain current path corresponds and the first power supply line; a precharge signal line commonly connected to the gates of the transistors; and a second power supply line arranged in the row direction on the one end side of the plurality of output lines, with a source-drain current path corresponding to one end of the source signal line and a second power supply line. a plurality of second field effect transistors of different conductivity types connected between the plurality of second field effect transistors; a signal line branched from the precharge signal line and commonly connected to the gates of the plurality of second field effect transistors; A plurality of memory cell field effect transistors selectively provided as a gate, each having a gate connected to one of the decoder lines, one of the output lines, and a source signal line corresponding to the unit to which this output line belongs. A plurality of memory cell field effect transistors each having a source-drain current path connected therebetween are provided, and an output signal for a selected decode line is taken out from the other end of the plurality of output lines.

(Example) Next, the present invention will be described in more detail with reference to the drawings.

An embodiment of the present invention is shown in FIG. 5, and a timing chart thereof is shown in FIG. 6. The contents of the ROM are of the N-channel horizontally stacked type as in the conventional example, and the N-channel MOS transistor 3 is formed at a predetermined portion between the source signal line and the output line.
The major feature in Figure 5 is that the source of the ROM cell consisting of the N-channel MOS transistor 3 is not directly connected to the ground, but the gate is connected to the precharge signal line PG and the source is connected to the ground.
It is connected to ground via a channel type MOS transistor 6. By adding this transistor, no current flows between V _DD and ground during precharge T1, and decode signals D0 to D3 are not inhibited during T1, and data transmission is delayed. There will be no more. Furthermore, since the N-channel MOS transistor 6 additionally added here only discharges the charge held by the stray capacitance, a large transistor is not required, and the semiconductor chip area increases due to the addition of this transistor. It's not that big. On the other hand, by adopting this configuration, wasteful current consumption is eliminated, and at the same time, there is no reduction in speed. As described above, the ROM configured according to the present invention has the effect of low current consumption and high speed. Moreover, as clearly shown in Figure 5, the P channel and N channel
Since MOS transistors 4 and 6 are placed together on one end side of output signal lines 00-03,
The wiring capacitance of the signal line that commonly connects the gates of the transistors 4 and the signal line that branches from the same signal line and commonly connects the gates of the transistors 6 is approximately equal.
As the level of the precharge signal PG changes, the conduction and cutoff states of transistors 4 and 6 change almost simultaneously, and high-speed operation is not hindered.
Further, based on the above arrangement of the MOS transistors 4 and 6, the output signals 00-03 are taken out from the other end of the output line as shown in the figure, and a circuit that utilizes the output signals 00-03 is directly provided at the other end. As a result, the wiring capacitance of each output line can be reduced accordingly, making it possible to achieve higher speeds.

[Brief explanation of drawings]

Figure 1 shows an example of a conventional ROM configuration.
Figure 2 is the timing chart. Figure 3 is a diagram showing an example of another conventional ROM configuration.
The figure shows the timing chart. FIG. 5 is a diagram showing an embodiment of the ROM of the present invention, and FIG. 6 is a timing chart thereof. 1...ROM main body, 2...decoder circuit, 3...
...N-channel MOS transistor which is a ROM cell, 4...P-channel MOS transistor,
5...AND circuit, 6...N channel type MOS transistor, A0, A1...input signal, D0, D
1, D2, D3...decoded output signal, O
0, O1, O2, O3...output signal, PG...precharge signal line.

Claims (1)

[Claims] 1 A plurality of decoder lines lined up in the row direction, a plurality of output lines lined up in the column direction, and two output lines adjacent to each other as one unit, and the column between the two output lines in each unit. one source signal line arranged in the row direction; first and second power supply lines arranged in the row direction on one end side of the plurality of output lines; a plurality of first field effect transistors of one conductivity type arranged in the row direction and connected between the one end of the output line to which the source-drain current path corresponds and the first power supply line; A commonly connected precharge signal line and a source-drain current path arranged in the row direction on the one end side of the plurality of output lines are connected between one end of the source signal line and the second power supply line. a plurality of second field effect transistors of different conductivity types, a signal line branched from the precharge signal line and commonly connected to the gates of the plurality of second field effect transistors; a plurality of memory cell field effect transistors provided, each with a gate connected to one of the decoder lines, and between one of the output lines and the source signal line corresponding to the unit to which this output line belongs; A read-only memory comprising: a plurality of memory cell field effect transistors having source-drain current paths connected to a plurality of memory cells, and an output signal for a selected decode line is taken out from the other end of the plurality of output lines.