JPH0412652U - - Google Patents
Info
- Publication number
- JPH0412652U JPH0412652U JP5294390U JP5294390U JPH0412652U JP H0412652 U JPH0412652 U JP H0412652U JP 5294390 U JP5294390 U JP 5294390U JP 5294390 U JP5294390 U JP 5294390U JP H0412652 U JPH0412652 U JP H0412652U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- lid
- semiconductor element
- shaped
- less
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Description
第１図は本考案の実施例１の断面図、第２図は
本考案の一実施例の斜視図、第３図は本考案の実
施例２の断面図である。
１……半導体素子、２，１２……金属板、３，
１３……基板、４，１４……接着剤、５，１５…
…外部導出用リード、６，１６……低融点ガラス
、７，１７……リツド。
1 is a sectional view of a first embodiment of the present invention, FIG. 2 is a perspective view of an embodiment of the present invention, and FIG. 3 is a sectional view of a second embodiment of the present invention. 1... Semiconductor element, 2, 12... Metal plate, 3,
13... Substrate, 4, 14... Adhesive, 5, 15...
...Lead for external extraction, 6,16...Low melting point glass, 7,17...Lead.
Claims (1)
板と前記半導体素子を覆うように前記基板に対し
て装着されたリツドと、前記基板と前記リツドと
の間に挟持されて外部に延長し、かつ前記半導体
素子に電気的に接続されたリードとを具備する半
導体装置において、前記基板は金属板で形成され
、前記リツドは厚み０．５mm以下の透光性アルミ
ナで形成され、かつ前記リードが所望の形状に整
形され、全体厚が１．３mm以下であることを特徴
とする紫外線透過型半導体装置。 A substrate on which an ultraviolet erasable memory semiconductor element is mounted, a lid attached to the substrate so as to cover the semiconductor element, and a lid that is sandwiched between the substrate and the lid and extends to the outside, and that extends outside the semiconductor element. In the semiconductor device, the substrate is formed of a metal plate, the lid is formed of transparent alumina with a thickness of 0.5 mm or less, and the lead is shaped into a desired shape. An ultraviolet transmitting semiconductor device characterized by being shaped and having an overall thickness of 1.3 mm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5294390U JPH0412652U (en) | 1990-05-21 | 1990-05-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5294390U JPH0412652U (en) | 1990-05-21 | 1990-05-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0412652U true JPH0412652U (en) | 1992-01-31 |
Family
ID=31573689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5294390U Pending JPH0412652U (en) | 1990-05-21 | 1990-05-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0412652U (en) |
-
1990
- 1990-05-21 JP JP5294390U patent/JPH0412652U/ja active Pending
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