JPH0412662B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is applicable to the field of control communication, for example, where a plurality of pieces of data are generated at any time, the state within a certain period of time is unchanged, and the period required by the next stage device is determined. Moreover, the present invention relates to a serial sequential transmitting device that transmits data sequentially in series.

Conventional configurations and their problems Recently, as society has become more sophisticated and complex, the need for advanced information and communication systems that can provide a large amount of information has been increasing. The system usually has a large number of information storage devices and a large number of terminal devices, and the control and communication of these devices is performed by a CPU (central processing unit).
It may also be networked. In such advanced information communication systems, the amount of communication control data is large and complex, and communication methods with high transmission speed and reliability are required. Especially in long-distance communication, there is a large possibility of signal delay, and data transmission It is necessary to devise a means to give a certain regularity to the method.

However, conventional data order transmitting devices are of a synchronous type having a shift register or counter, or of an asynchronous type such as an arbiter in a multiprocessor system. Therefore, the former synchronous method requires a sampling clock and shift pulses, and because reception and transmission are synchronized, clocks and shift pulses with a cycle faster than the serial sequential transmission cycle cannot be used, and regardless of the presence or absence of data, It was necessary to check all data lines in order, making it difficult to increase the data reception cycle speed. Furthermore, a synchronization signal was required to synchronize transmission and reception.

Furthermore, the latter arbiter also needs to check the request signals of all cells, which requires time and shift pulses, making it difficult to increase the data transmission cycle speed.

Purpose of the Invention The present invention was made in view of the above-mentioned problems, and its purpose is to enable high-speed reception and transmission without requiring a sampling clock or shift pulse for data reception. The present invention provides a serial sequential transmitter that can transmit data in synchronization with an arbitrary transmission cycle without requiring a synchronizing signal for synchronizing reception and transmission.

Structure of the Invention The present invention includes a first buffer memory that temporarily stores a plurality of received data generated from time to time, and a first selection means that gives a first priority to the plurality of received data stored in the first buffer memory. a second buffer memory for temporarily storing a plurality of received data preferentially selected by the first selection means; and a second buffer memory for giving a second priority to the plurality of received data stored in the second buffer memory. and a data erasing means for erasing the received data stored in the first and second buffer memories in synchronization with the data transmission cycle when the data is transmitted to the next stage device. This enables synchronized transmission, which transmits data in synchronization with any transmission cycle required by the next-stage device, without depending on the data reception cycle. Since it is no longer necessary, the circuit becomes simpler, the device becomes smaller, and it becomes easier to adapt to any next-stage receiving device.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

As an embodiment of the present invention, a case where the present invention is applied to a VTR control device (hereinafter abbreviated as VTRC) will be described.

FIG. 1 shows a VTR control system configuration diagram, and FIG. 2 shows a VTR control system communication diagram showing the types of communication data and signals required to control the above system and their flows.

In Figures 1 and 2, VTRC20 is
Receives command data from the CPU 10, and based on the data sends switch signals 51a to 74a to, for example, 24 VTRs 30,
LAMP signal 5 representing VTR dynamics of VTR group 30
1ro to 74ro and cue tones 51c to 74c representing the running position of the VTR tape are received, and the VTR dynamic changes and cue signals are sent to the CPU 10 as status data, and the VTR tape is sent to the CPU 10 as status data.
Display the dynamics of Here, as shown in FIG.
It consists of a VTR address and command 43, and status data is an iRT (interrupt) signal 44.
It consists of VTR address and status 45. Furthermore, FIG. 3 shows a bitmap of communication data between the CPU and VTRC. Here, for both upstream data B and downstream data A, only the VTR addresses 43a and 45a are binary numbers, and the others correspond to bits. Also
The ACK (Acknowledge) signal 46 is generated when the CPU 10 completes receiving status data.
An RDY (Ready) signal 41 indicates a state in which the VTRC 20 is ready for reception. Note that in the above system, four types of commands and five types of status are communicated.

In the above configuration, command data transmitted from the CPU 10 is first received by the receiver 100. The receiver 100 decodes the VTR address 43a in the command data and generates a switch signal 141 for each VTR and also for each command 43b. This switch signal 141 is transmitted to the VTR switch isolator 200. The VTR switch isolator 200 electrically isolates the VTRC 20 from the VTR group 30, converts the signal level, and sends a VTR switch signal 231 to each VTR in the VTR group 30.

On the other hand, VTRLAMP signal 3 indicating the dynamics of each VTR
11 is input to the VTRLAMP isolator 300. This isolator 300 is connected to the VTR group 30.
In addition to electrically insulating VTRC20 and converting the signal level, it also converts the status 45b.
It generates a STOP signal and a PLAY signal, and transmits the status signal 341 to the status display 400 and transmitter 600. Incidentally, this status signal 341 is a signal that changes in synchronization with changes in the dynamic state of the VTR, and while the VTR maintains one dynamic state, the status signal 341 is also held and does not change.
Further, a cue tone 511 representing the running position of the VTR tape is input to the cue signal generator 500.
Therefore, the cue signal generator 500 outputs signals to each of the VTR group 30.
It electrically isolates the audio output terminal of the VTR and the VTRC20, amplifies the audio signal level, detects the audio signal, checks its duration, and if the signal exceeds the set time, a TTL level cue signal 541 and further generates a cue signal 54
1 to transmitter 600.

Finally, the transmitter 600 receives the plurality of status signals 341 and the plurality of cue signals 541 at any time and in parallel. Upon this reception, the transmitter 600 encodes the received signal, that is, generates a VTR address 45a for distinguishing the VTR in the VTR group 30 that is the source of the received signal, and also generates an iRT signal 44.
The status data is transmitted in synchronization with the ACK signal 46, and if the ACK signal 46 is not received, the status data is transmitted at a set cycle.
This status data is synchronized with CPU10.
Sent to CPU 10.

Control communication of the VTR control system is performed as described above.

Next, the operation of each part of the transmitter 600 will be explained based on FIG. 4 showing the blocks of the transmitter 600 and the flow of signals.

First, the multiple status signals 341 and
Cue signals 541 are input to independent input buffers 71
It is input in parallel to 0. These status signals 341 and cue signals 541 are generated at any time and
It is a signal that has the property that it remains unchanged for a certain period of time when it maintains one dynamic state. Therefore, consideration must also be given to the case where a plurality of signals are received simultaneously.

Next, the status signal 341 and the cue signal 541
is the first stage buffer memory 8 in the priority transfer circuit 800 via the input buffer 710.
It is input to the CK (clock) terminal of each of the 10 cells. Here, in this system, since the D (data) terminal of each cell of the buffer memory 810 is not used, the status signal 341 and the cue signal 541 are sent to the buffer memory 810 at the same time as they are generated.
The output of each cell is stored in each cell, and the output of each cell is stored in a primary line selection element 8 having a priority function.
20. At any time, the line selection element 820 outputs only the highest priority signal among the plurality of simultaneously input signals according to a predetermined priority order. The output signal of the line selection element 820 is input to each cell CK terminal of the second stage buffer memory 830 and stored therein. Here again, the D terminal of buffer memory 830 is not used. The output signal of buffer memory 830 is input to encoder 840 having a priority function. The system uses encoder 840 as a secondary line selection element. Here, as described above, the line priority order set by the primary line selection element 820 is completely opposite to the line priority order determined by the encoder 840. (In the above, the portion consisting of buffer memory 810, primary line selection element 820, buffer memory 830, and encoder 840 is priority transfer circuit 800, and a specific basic circuit thereof is shown in FIG. 5. ) Here, the reason why the priority order of the secondary line selection element 840 is reversed to that of the primary line selection element 820 will be explained.

Among the signals input to the primary line selection element 820 at that time, the highest priority signal, for example, S3
is stored in the second stage buffer memory 830, input to the encoder 840, and output to the CPU. Here, if S1, which has a higher priority than S3, is input at the input point of the primary line selection element 820 before the CPU reads the data of S3, the output line of the primary line selection element 820 will be set to S1. 2nd stage buffer memory 830
is memorized. (Note that the primary line selection element 82
When S4, which has a lower priority than S3, is input at the input point 0, the output line of the primary line selection element 820 remains unchanged, and the contents stored in the second stage buffer memory 830 do not change. ). S1 and S3 are output from the second-stage buffer memory 830, but since the priority of the secondary line selection element 840 is reversed to that of the primary line selection element 820 (that is, S3 is has a higher priority than S1), S1 does not appear in the output of the encoder 840, and the data in S3 can be output as is without being lost.

In other words, the function of the priority order in reverse order is such that even if a signal with a high priority order comes later and is stored in the second stage buffer memory 830 (a signal with a low priority order is stored in the second stage buffer memory 830 by the action of the first line selection element 820, The signals are output in the order in which they are input to the second stage buffer memory 830 due to the action of the secondary line selection element 840 (not input to the second stage buffer memory 830).

Next, the output signal encoded by the encoder 840, that is, the address signal 840a, and the GS (Groupe
Select) output signals 840b are both passed through an output buffer 760, in which case the address signal 84
0a is the signal for the lower three digits of the VTR address 45a, and the GS output signal 840b is the status 4 signal.
5b is sent to the CPU 10. on the other hand,
Address signal 840a and GS signal 840b are transferred to clear data memory 740 as data to be stored. Further, the GS signal 840b is sent to the secondary encoder 73 via the address switch 720.
Input to 0. Here address switch 720
is a manual switch for dividing the VTR group 30 into groups of eight VTRs and setting the group number in advance. Also encoder 730
encodes the signal of the line set by the address switch 720, and the output signal encoded by the encoder 730 is sent via the output buffer 760.
As the signal of the upper 3 digits of VTR address 45a
Sent to CPU 10. Next, encoder 73
The GS signal of 0 is input to the interrupt controller 900, and the one shot pulse generated using this as a trigger is input to the output buffer 760 and is output as the iRT signal.
The one shot pulse is input to the clock terminal of the clear data memory 740, and the address signal 8 of the encoder 840 is sent to the CPU 10.
40a and the GS signal 840b serve as clock signals for the clear data memory 740 to store. The signal stored in the clear data memory 740 is then input to the output line selection terminal of the data clear signal generator 750. Next, CPU10
transmits an ACK signal 46 to the transmitter 600 when it completes receiving the status data, and
Signal 46 is input to interrupt controller 900 via input buffer 710. The one shot pulse generated using this ACK signal 46 as a trigger is input to the Enable terminal of the data clear signal generator 750, and using this as a trigger, the data clear signal generator 750 generates a data clear signal 751.
The data clear signal is sent to the buffer memory 810,
830 and clears the data in each cell storing the status signal corresponding to the status data transmitted to the CPU 10. The interrupt controller 900 as described above transmits status data to the CPU 10 in synchronization with the status signal,
The status signal is also cleared in synchronization with the ACK signal 46. Here, the transmitter 600
Generates iRT signal 44 and buffer memory 810, 8
If the time required to clear 30 stored data is defined as one unit, if the transmitter 600 receives multiple status signals in this unit time, when the interrupt controller 900 clears the transmitted status signal, At the same time, the encoder 840 outputs the status signal with the next priority, and the status data is processed through the same procedure as described above.
Sent to CPU 10. In this way, the status data is sequentially transmitted in synchronization with the ACK signal 46.

Hereinafter, this transmission synchronous serial order transmission system will be described in detail with reference to the drawings.

FIG. 5 shows the basic circuit of the priority transfer circuit 800. The input signals S1-S8 of this circuit are status signals 341. The first stage buffer memory 810 has eight cells, each of which has eight cells.
A status signal 341 is input to the CK (clock) terminal via an input buffer 710, and each D (data) terminal is pulled up to +5V. As a result, the status signals S1 to S8
As soon as the signal is generated, it is stored in each cell of the buffer memory 810, and the transmitter 6 including this circuit does not require a sampling clock.
Data can be collected without the need to synchronize with the transmission cycle of 00. Next, the status signal is stored in buffer memory 810, and at the same time its outputs Q1-Q8 are input to primary line selection element 820 having a priority function. This line selection element 820 determines the output priority of the input signals and outputs only the most significant input signal at any time, even when a new signal is input. Therefore, if the order of the new input signal is higher than all the orders of the plurality of signals that have already been input, the new input signal will be output, and in this case, the output signal of the line selection element 820 will be output when the status signal is input. will change. Furthermore, when the highest input signal among a plurality of input signals disappears, the input signal of the next rank is outputted, and in this case, when the status signal stored in the buffer memory 810 is erased, the line selection element The output signal of 820 will change. Here, the VTR address status 45 sent to the CPU 10 must be maintained during the data reading period of the CPU. If the new input signal to the line selection element 820 is higher in rank than all the existing input signals, the second one is added to ensure that the signal that is being output at the time of input of the new input signal is transmitted without being lost. Level buffer memory 8
30 and encoder 8 with priority function
It is 40. As for the signal output priority of the line selection element 820, Y1 has the highest priority, and the priorities are sequentially lowered, with Y8 being set as the lowest. Therefore, Y
The first priority order of the status signals S1 to S8 corresponding to the status signals S1 to Y8 is that S1 has the highest priority, and the priority rankings decrease sequentially thereafter, and S8 is the lowest. These output signals Y
1 to Y8 are CK1 to CK8 of buffer memory 830
is input. Since the data input terminals D1 to D8 of the buffer memory 830 are pulled up to +5V, at the same time as signals are input to CK1 to CK8, those signals are transferred to the buffer memory 830.
are stored in each cell and simultaneously output from cells 1 to 8. The output signals 1 to 8 of the buffer memory 830 are input to the input terminals 0 to 8 of the encoder 840.
7 is input. This encoder 840 determines the output priority order of the input signals, encodes the highest input signal into a binary number, and outputs the encoded signal. Therefore, among the plurality of signals stored in the buffer memory 830, only the highest ranked signal determined by the encoder 840 is output, and even if the output signal of the line selection element 820 changes, the signal is not stored in the buffer memory 830. encoder 84 unless the signal is erased.
The output signal of 0 does not change. Furthermore, when the most significant signal held by the buffer memory 830 is erased, the next most significant signal is encoded into a binary number and output. Here, the input signals 0 to 7 of the encoder 840 are
The output priority order is set to be completely opposite to the order of the line selection element 820, with 7 being the highest, and the subsequent orders decreasing sequentially, with 0 being the lowest. Therefore, in the secondary priority order of the status signals S1 to S8 corresponding to 0 to 7, S8 has the highest priority, and the priority rankings decrease sequentially thereafter, with S1 being the lowest. In this way the status signal S1
By setting the output priorities of S8 to be completely opposite for the first and second outputs, it becomes possible to hold the data during the data reading period of the CPU 10. This priority transfer method will be specifically explained below.

First, the plurality of status signals S1 to S8 are
If input in the next priority order or at the same time, all signals are stored in buffer memory 810 and input to line selection element 820. And the first
Only the highest priority signal is output from the line selection element 820, stored in the buffer memory 830, and input to the encoder 840.
It is encoded into a base number and sent to the CPU 10. Then, when the reception of CPU10 is completed, CPU10
transmitting the ACK signal 46 to the transmitter 600;
Simultaneously with receiving the ACK signal 46, the data clear signal generator 750 generates a data clear signal 751. This data clear signal 751 is for erasing the most significant signal sent earlier, and is simultaneously input to the CLR terminals of the cells of buffer memories 810 and 830 that store the most significant signal.
The most significant signal is erased. When the most significant signal is erased, the next highest signal is output from the line selection element 820, stored in the buffer memory 830, and output from the encoder 840. In this way, the signals are sequentially transmitted to the CPU 10.
Next, when the plurality of status signals S1 to S8 are input according to the second priority order, that is, in the reverse order of the first priority order, all the signals are input to the buffer memory 81.
It is accumulated to 0 and is all output from the line selection element 820. Then, all the signals are stored in the buffer memory 830 and the encoder 8
40 are all input. Here, the encoder 84
0 outputs only the highest secondary priority signal among a plurality of input signals. Therefore, in this case, the output of the line selection element 820 changes at the same time as a new signal is input, but since all input signals are stored in the buffer memory 830, the output of the encoder 840 does not change, which is the same as in the previous case. Similarly, the transmitter 600 receives the ACK signal 46, and sends it to the buffer memory 810 corresponding to the transmitted data.
and the accumulated signal of 830 as the data clear signal 751
The output signal of encoder 840 is held until erased. Then, when the highest input signal of the encoder 840 is erased, the next highest input signal is outputted from the encoder 840. In this way, all the signals are sequentially transmitted to the CPU 10.

Finally, during the signal transmission period, that is, from the time when one signal is transmitted from the encoder 840 to the CPU 10,
Consider a case where a plurality of status signals S1 to S8 are input during the period from when the CPU 10 completes reception and transmits the ACK signal 46 to when the transmitted signal is cleared by the data clear signal 751. In this case, the priority transfer of the input signal whose primary priority is higher than the signal being transmitted is the same as in the two cases described above. However, the signal that is being transmitted is
When a signal with a lower next priority is input, all of the lower signals are blocked by the line selection element 820 and transferred according to the first priority, regardless of their input order.

As described above, the transmission order of the status signals S1 to S8 is determined by the first or second priority function, and one transmission is performed during the data reading period of the CPU 10 regardless of the order and time in which the status signals are generated. Only the data is retained,
All status signals are sequentially transmitted in synchronization with the ACK signal 46 transmitted by the CPU 10, that is, in a transmission synchronous manner.

Effects of the Invention As described above, in the present invention, the first stage buffer memory can receive multiple pieces of data that are generated at any time and whose state remains unchanged for a certain period of time, and the first stage buffer memory has a priority function. When combined with a selection means, there is no need for a sampling clock or a shift pulse for data acquisition, and the data line can be checked using only the data generation line, making it possible to receive a plurality of data at high speed and simultaneously. Furthermore, by providing a second buffer memory and a second line selection means with a priority function, there is no need to shift pulses for transmission and there is no need to check data lines with no signal, increasing the speed of data transmission. becomes possible. In addition, by arranging the combination of buffer memory and line selection means with priority function in two stages as described above, it is possible to synchronize with any transmission cycle required by the next stage equipment without depending on the data reception cycle. Transmission synchronous transmission that transmits data is now possible.
Further, by providing data erasing means having a function of simultaneously erasing data in the first and second buffer memories in synchronization with the transmission cycle, a synchronization signal for synchronizing reception and transmission can be made unnecessary. In addition, since sampling clocks, shift pulses, or synchronization signals are no longer required, the circuit becomes simpler and the equipment becomes smaller, the probability of malfunctions due to noise is lowered, and furthermore, it is compatible with all next-stage receiving equipment. The effects are great, such as making things easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a VTR control system to which a serial order transmitter according to an embodiment of the present invention is applied, FIG. 2 is a block diagram of main parts of the same VTR control system, and FIGS. A diagram showing a VTRC communication data bitmap, FIG. 4 is a block diagram of the transmitter, and FIG. 5 is a block diagram of the basic priority transfer circuit. 10...CPU, 20...VTR control device, 60
0...Transmitter, 800...Priority transfer circuit, 810...First stage buffer memory, 820...Line selection element, 830...Second stage buffer memory
Stage buffer memory, 840...encoder.

Claims (1)

[Claims] 1: a first buffer memory for temporarily storing a plurality of received data generated from time to time; a first selection means for giving a first priority to a plurality of received data stored in the first buffer memory; a second buffer memory for temporarily storing a plurality of received data preferentially selected by the selection means;
a second selection means for giving a second priority to the plurality of received data stored in the buffer memory of the buffer memory; data erasing means for erasing the received data stored in the second buffer memory, the data erasing means for erasing the received data stored in the second buffer memory; A serial sequential transmitter characterized in that it receives data in parallel and transmits the data in synchronization with an arbitrary transmission cycle required by a device at the next stage without depending on the data reception cycle.