JPH0412663B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is applicable to the field of control communication, for example, where a plurality of pieces of data are generated at any time, the state within a certain period of time is unchanged, and the period required by the next stage device is determined. Moreover, it relates to a serial data receiving device that transmits data in series.

Conventional configurations and their problems Recently, as society has become more sophisticated and complex, the need for advanced information and communication systems that can provide a large amount of information has been increasing. The system usually has a large number of information storage devices and a large number of terminal devices, and the control and communication of these devices is performed by a CPU (central processing unit).
It may also be networked. In such advanced information communication systems, the amount of communication control data is large and complex, and communication methods with high transmission speed and reliability are required. Especially in long-distance communication, there is a large possibility of signal delay, and data transmission It is necessary to devise a means to give a certain regularity to the method.

However, conventional serial data transmitting devices are of a synchronous type having a shift register or counter, or of an asynchronous type such as an arbiter in a multiprocessor system. Therefore, the former synchronous method requires a sampling clock and shift pulses, and because reception and transmission are synchronized, clocks and shift pulses with a cycle faster than the serial transmission cycle cannot be used, and regardless of the presence or absence of data, all You need to check the data line of
It has been difficult to increase the data reception cycle speed. Furthermore, a periodic signal was required to synchronize transmission and reception.

Furthermore, the latter arbiter also needs to check the request signals of all cells, which requires time and shift pulses, making it difficult to increase the data transmission cycle speed.

Purpose of the Invention The present invention was made in view of the above-mentioned problems, and its purpose is to enable high-speed reception and transmission without requiring a sampling clock or shift pulse for data reception. Moreover, the present invention provides a serial transmitter that can transmit in synchronization with any transmission cycle without requiring a synchronization signal for synchronizing reception and transmission.

Structure of the Invention The present invention includes a first latching means for received data, a first priority line selection means, a second latching means for secondary priority, and a first priority line selection means. , relates to a device equipped with a clear data memory, a data clear signal generating means, and an interrupt controller, and is characterized by having an interrupt control device that transmits data in synchronization with an arbitrary transmission cycle or with a self-cycle. That is.

That is, the first latch means stores received data at the same time as it is generated, making it possible to receive a plurality of pieces of data that do not require a state within a certain period of time and to receive them simultaneously at high speed. Further, the first line selection means determines the primary priority of the data stored by the first latch means, and transfers only the data with the highest priority. The second latch means stores the data selected by the first line selection means for a certain period of time, and erases the data even if the output signal of the first line selection means changes before data transmission is completed. Allows for transfer without any hassle. The second line selection means determines the secondary priority of the data stored by the second latch means, and transmits only the data with the highest priority. However, the priority order of the first order and that of the second order are completely opposite, and the selected data is held until its transmission is completed. The clear data storage means stores the data sent to the CPU and sends it to the data clear signal generation means. The data clear signal generating means generates a signal for clearing the data received by the CPU and transmits it to the first and second latch means when the CPU completes reception. The interrupt control means receives an AC signal from the CPU and generates an interrupt signal in synchronization with the AC signal, and
It controls the clear data storage means and the data clear signal generation means, and performs interrupt control using a self-cycle when an ACK signal is not received.

With the above configuration, it is possible to perform transmission synchronous transmission in which data is transmitted in synchronization with any transmission cycle required by the next stage device without depending on the data reception cycle. Since a shift pulse or a synchronization signal is no longer necessary, the circuit becomes simple and the device becomes compact, and furthermore, it becomes easy to adapt to any next-stage receiving device.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

As an embodiment of the present invention, a case where the present invention is applied to a VTR control device (hereinafter abbreviated as VTRC) will be described.

FIG. 1 shows a VTR control system configuration diagram, and FIG. 2 shows a VTR control system communication diagram showing the types of communication data and signals required to control the above system and their flows.

In Figures 1 and 2, VTRC20 is
Receives command data from the CPU 10, selects switch signals 51A to 74A to, for example, a group of 24 VTRs based on the data, and
LAMP signals 51-74 represent the dynamics of the VTR in group 30 and the running position of the VTR tape.
Cue tones 51-74 are received,
The dynamic change of the VTR and the cue signal are sent to the CPU 10 as status data, and the dynamic state of the VTR is displayed. Here, as shown in FIG. 2, the command data is connected to the STB (strobe) signal 42.
It consists of a VTR address and command 43, and status data is an iRT (interrupt) signal 44.
It consists of VTR address and status 45. Furthermore, FIG. 3 shows the bit up of communication data between the CPU and VTRC. Here, for both upstream data B and downstream data A, only the VTR addresses 43a and 45a are binary numbers, and the others correspond to bits. Also
The ACK (Acknowledge) signal 46 is generated when the CPU 10 completes receiving status data.
An RDY (Ready) signal 41 indicates a state in which the VTRC 20 is ready for reception. In the above system, four types of commands and five types of status are communicated.

In the above configuration, command data transmitted from the CPU 10 is first received by the receiver 100. The receiver 100 decodes the VTR address 43a in the command data and generates a switch signal 141 for each VTR and also for each command 43b. This switch signal 141 is transmitted to the VTR switch isolator 200. The VTR switch isolator 200 electrically isolates the VTRC 20 and the VTR group 30, converts the signal level, and selects a VTR switch signal 231 to each VTR of the VTR group 30. It also shows the dynamics of each VTR.
VTRLAMP signal 311 is input to VTRLAMP isolator 300. This isolator 30
0 electrically isolates the VTR group 30 and VTRC 20 and converts the signal level, and status 4
Generate the STOP signal and PLAY signal of 56,
The status signal 341 is transferred to the status indicator 400
and is transmitted to the transmitter 600. Incidentally, this status signal 341 is a signal that changes in synchronization with changes in the dynamic state of the VTR, and while the VTR maintains one dynamic state, the status signal 341 is also held and does not change. Further, a cue tone 511 representing the running position of the VTR tape is input to the cue signal generator 500. This cue signal generator 500 is a VTR
The audio output terminal of each VTR in group 30 is electrically isolated from the VTRC 20, the audio signal level is amplified, the audio signal is detected, and its duration is checked, and if the signal exceeds the set time,
Generates a TTL level cue signal 541, and further
Cue signal 541 is transmitted to transmitter 600.

Finally, the transmitter 600 receives the plurality of status signals 341 and the plurality of cue signals 541 at any time and in parallel. Upon this reception, the transmitter 600 encodes the received signal, that is, it encodes the received signal in the VTR group 30 that is the source of the received signal.
Generates a VTR address 45a for distinguishing between VTRs, and generates an iRT signal 44.
The status data is transmitted in synchronization with the ACK signal 46, and further, the status data is transmitted at a set cycle when the ACK signal 46 is not received.
This status data is synchronized with CPU10.
Sent to CPU 10.

Control communication of the VTR control system is performed as described above.

The operation of each part of the transmitter 600 will be explained below based on FIG. 5 showing the blocks of the transmitter 600 and the flow of signals.

First, the multiple status signals 341 and
Cue signals 541 are input to independent input buffers 71
It is input in parallel to 0. These status signals 341 and cue signals 541 are generated at any time and
It is a signal that has the property that it remains unchanged for a certain period of time when it maintains one dynamic state. Therefore, consideration must also be given to the case where a plurality of signals are received simultaneously.

Next, the status signal 341 and the cue signal 541
is input to the CK (clock) terminal of each cell of the primary latch element 810 in the priority transfer circuit 800 via the input buffer 710. Here, in this system, the D (data) terminal of each cell of the latch element 810 is not used, so
The status signal 341 and the cue signal 541 are stored in each cell of the latch element 810 at the same time as they are generated, and the output of each cell is input to a primary line selection element 820 having a priority function. At any time, the line selection element 820 outputs only the highest priority signal among the plurality of simultaneously input signals according to a predetermined priority order.
The output signal of line selection element 820 is input to the CK terminal of each cell of secondary latch element 830 and stored. Again, the output signal of latch element 830 is input to encoder 840 having a priority function. The system uses encoder 840 as a secondary line selection element. Here, as described above, the primary line selection element 820
The line priority determined by the encoder 840 is completely opposite to the line priority determined by the encoder 840.

Here, the reason why the priority order of the secondary line selection element 840 is reversed from that of the primary line selection element 820 will be explained.

Among the signals input to the primary line selection element 820 at that time, the highest priority signal, for example, S3
is stored in the second stage buffer memory 830, input to the encoder 840, and output to the CPU. Here, if S1, which has a higher priority than S3, is input at the input point of the primary line selection element 820 before the CPU reads the data of S3, the output line of the primary line selection element 820 will be set to S1. and is stored in the second stage buffer memory 830. (Note that the primary line selection element 820
If S4, which has a lower priority than S3, is input at the input point of
(No change is made to the memory contents of 30). S1 and S3 are output from the second-stage buffer memory 830, but since the priority of the secondary line selection element 840 is reversed to that of the primary line selection element 820 (that is, S3 is has a higher priority than S1), and the output of encoder 840 has S1.
1 does not appear, and the data in S3 can be output as is without being lost.

In other words, the function of the priority order in reverse order is such that even if a signal with a high priority order comes later and is stored in the second stage buffer memory 830 (a signal with a low priority order is stored in the second stage buffer memory 830 by the action of the first line selection element 820, The signals are output in the order in which they are input to the second stage buffer memory 830 due to the action of the secondary line selection element 840 (not input to the second stage buffer memory 830).

Next, the output signal encoded by the encoder 840, that is, the address signal 840a, and the GS (Groupe
Select) output signals 840b are both sent to the CPU 10 via an output buffer 760.

At this time, the address signal 840a is used as the lower three digit signal of the VTR address 45a, and also as the GS
The output signal 840b is sent to the CPU 10 as one of the statuses 45b. On the other hand, address signal 840a and GS signal 840b are transferred to clear data memory 740 as data to be stored.
Furthermore, the GS signal 840b is sent to the address switch 7.
20 to a secondary encoder 730. Here, the address switch 720 is set to VTR group 3.
This is a manual switch for dividing 0 into groups of 8 VTRs and setting the group numbers in advance. Further, the encoder 730 encodes the line signal set by the address switch 720, and the output signal encoded by the encoder 730 is sent to the VTR address 45a via the output buffer 760.
It is sent to the CPU 10 as a signal of the upper three digits.
Next, the GS signal of the encoder 730 is input to the interrupt controller 900, and the one shot pulse generated using this as a trigger is input to the output buffer 760 and transmitted to the CPU 10 as an iRT signal, while the one shot pulse is used as clear data. It is input to the clock terminal of memory 740 and encoder 8
40 address signals 840a and GS signals 840b
This becomes a clock signal for the clear data memory 240 to store. The signal stored in the clear data memory 740 is then input to the output line selection terminal of the data clear signal generator 750. Next, when the CPU 10 completes receiving the status data, it sends an ACK signal 46 to the transmitter 6.
00, signal 46 to AC is input buffer 7
10 to the interrupt controller 900. The one-shot pulse generated using this ACK signal 46 as a trigger is sent to the data clear signal generator 750.
The data clear signal generator 750 generates the data clear signal 751 using this as a trigger, and the data clear signal is sent to the latch elements 810 and 830, and the data clear signal generator 750 generates the data clear signal 751.
The data in each cell that stores the status signal corresponding to the status data sent to is cleared. As described above, the interrupt controller 900
Status data synchronized with status signal
It is transmitted to the CPU 10 and also clears the status signal in synchronization with the ACK signal 46. Here, if the time from when the transmitter 600 generates the iRT signal 44 to when the data stored in the latch elements 810 and 830 is cleared is defined as one unit, if the transmitter 600 receives multiple status signals in this unit time, At the same time as the interrupt controller 900 clears the transmitted status signal, the encoder 840 outputs the status signal with the next priority, and the status data is transmitted to the CPU 10 through the same procedure as described above. In this way, the status data is sequentially transmitted in synchronization with the ACK signal 46.

This transmission synchronous serial data transmission system will be described in detail below with reference to the drawings.

FIG. 6 shows a signal flowchart of the interrupt control circuit. All of the status signals 831 stored in the secondary latch element 830 are input to a priority encoder 840, and only the signal with the highest secondary priority among them is output. The output signals are binary encoded signals 840a ₀ to _{a 2} and a GS (Groupe Select) signal 84 indicating the presence or absence of an input signal.
Output as 0b. This GS signal 840b is a signal indicating the group to which the VTR that generated the status signal 831 belongs, and since the status signal 831 is the same type of signal, for example, a status signal of PLAY, the CPU 1
It is also the status 456 sent to 0. on the other hand,
Binary signals 840a ₀ to a ₂ are in the same group.
This is a signal indicating the relative address of the VTR, and is a signal that indicates the relative address of the VTR.
0 as the last three digits of the VTR address 45a. These four signals, GS signal 84
0b and binary signals 840a ₁ -a ₂ are transmitted to clear data memory 240 and latched in clear data memory 740 for a fixed period of time starting from a certain point. moreover
GS signal 840b is data clear signal generator 75
0 is enabled and transmitted to the address switch 720. This address switch 720 generated a status signal 831.
This is to set the group number to which the VTR belongs in advance, and the above GS signal 840b
is input to the input terminal of encoder 730 corresponding to the line set by address switch 720. And the encoder 730 outputs the GS signal 84
A signal obtained by encoding 0b into a binary number and a GS signal 730b indicating the presence or absence of an input signal are output. The former binary signal is the VTR address 45 sent to the CPU 10.
It is transmitted to the CPU 10 as a signal of the upper three digits of a. On the other hand, the latter GS signal 730b is transmitted to the interrupt controller 9
It is input to the trigger input terminal 1A of 00. Here, the interrupt controller 900 is an element that includes two monostable multivibrator circuits, each having two trigger input terminals A and B, two output terminals Q, and one CLR (clear) terminal. , 1A, 1B, 1Q, 1 and 1CLR are for the first circuit, and 2A, 2B, 2Q, 2 and 2CLR are for the second circuit. As shown in the figure, 2A is grounded and 2CLR is pulled up to +5V.
Furthermore, 1 is input into 2B and 2 is input into 1B. Furthermore, in both the first and second circuits,
When trigger input terminal B is at high level, it is triggered at the falling edge of the signal input to trigger input terminal A, while trigger input terminal A
When is at a low level, each trigger is triggered at the rising edge of the signal input to the trigger input terminal B, and the output terminals Q and of the first and second circuits output a one-shot pulse signal. Here, the output signal Q is a high level pulse, and the output signal is a low level pulse. Therefore, since the 1B terminal of the interrupt controller 900 is initially at a high level, the interrupt controller 900 outputs the first signal at the time when the encoder 730 generates the GS signal 730b.
The circuit is triggered and outputs a one-shot pulse signal from the 1Q, 1 terminal. The output signal of 1Q is appropriately delayed by the delay circuit 910, and is sent to the CPU 10 as the iRT signal 44 via the output buffer, and also sent to the CK of the clear data memory 740.
This is input to the terminal and becomes a trigger signal to output signals 840b and 840a ₁ of the encoder 840.
~a ₂ is latched into clear data memory 740. Next, the output signal 1 of the interrupt controller 900 is input to 2B, and the second circuit is triggered when the output signal 1 rises, that is, the time set by the first circuit constant has elapsed. The interrupt controller 900 outputs a one-shot pulse signal from 2 to Low level. This second output signal is the Enable terminal G of the data clear signal generator 750.
Input to 2A. Therefore, at the same time that the second output pulse is generated, the data clear signal generator 750
Data clear signal 75 from the selected output terminal of
1 occurs. Line selection data A, B, and C of the data clear signal generator 750 are latch outputs of the clear data memory 740, and are the same as the data sent to the CPU 10. Therefore, the data clear signal 751 is input to the CLR (clear) terminal of the corresponding cell of the first and second latch elements storing the data transmitted to the CPU 10, and erases the stored data. As described above, the status signal 831 is transmitted to the CPU and is erased after the set time has elapsed.

Here, a case will be described in which the CPU 10 receives the ACK signal 46, which is transmitted as a data reception completion signal, within the set time. Interrupt controller 900
The 1Q output signal of is delayed by the delay circuit 910 and sent to the CPU 10 as the iRT signal 44 via the output buffer.
, the CPU 10 reads the status data (VTR address status) at the falling edge of the iRT signal, that is, when the signal is generated, and when the arithmetic processing is completed.
An ACK signal 46 is transmitted. This ACK signal is input to the 1CLR terminal of the interrupt controller 900. At this input point, the 1Q, 1 output signal of the interrupt controller 900 is cleared and returns to the initial state. In other words, 1Q is
1 becomes a low level, and 1 becomes a high level. Furthermore, the point at which 1 changes to High level, that is,
At the input of the ACK signal 46, the second circuit is triggered and a pulse is output from 2. The subsequent operations are as described above. In this way, ACK
Data can be transmitted and erased regardless of whether or not the signal 46 is input.

Next, within the unit transmission time of the status signal 831, that is, within the time from when the first circuit output of the interrupt controller 900 is generated until the second circuit output disappears, the plurality of status signals 831 are continuously transmitted. A case where the signal is input to the primary encoder 840 will be explained. As described above, the data clear signal 751 is generated at the same time as the output signal 2 of the interrupt controller 900 is generated, and when the data sent to the CPU 10 is cleared, the data with the next priority is output from the encoder 840. The output signal is the second
Next, the GS signal 730b is input to the encoder 730.
is input to 1A of the interrupt controller 900 (at this point, there is still a signal output period of 2), 1B is
Since the level is low, the first circuit is not triggered. Since 1A is at a low level at the end of the second output signal, the first circuit is triggered at this point, and the iRT signal 44 is activated.
Sent to CPU. Furthermore, if the output period of the ACK signal 46 is longer than the output period of 2, the first circuit is not triggered at this point because 1CLR is at a low level at the end of the output of 2.
At the end of the ACK signal, 1A is low level and 1
Since B is at a high level, the first circuit is triggered at this point, and the output signal of 1Q is transmitted to the CPU 10 as an iRT signal. In this way,
Regardless of the length of the generation period of the ACK signal 46,
During the ACK signal generation period, the iRT signal 44 is sent to the CPU 10.
The method is not to send to.

In the above way, multiple consecutive input signals can also be
It is possible to transmit data serially in synchronization with the transmission cycle required by the CPU 10, that is, in a transmission synchronous manner.

Effects of the Invention As described above, according to the present invention, the first latch means makes it possible to receive a plurality of pieces of data that are generated at any time and whose state remains unchanged for a certain period of time, and furthermore, the first latch means has a priority function. By combining this with a line selection means, there is no need for a sampling clock or shift pulse for data collection, and the data line can be checked using only the data generation line, making it possible to receive multiple data at high speed and simultaneously. Furthermore, by providing the second latch means and the second line selection means having a priority function, there is no need for a shift pulse for transmission and there is no need to check data lines with no signal.
It has become possible to speed up data transmission. Further, as described above, the combination of the latch means and the line selection means having the priority function is arranged in two stages,
Furthermore, by providing an interrupt control means that has a function of simultaneously erasing the data accumulated by the first and second latch means in synchronization with the transmission cycle, a synchronization signal for the reception and transmission synchronization ratio is eliminated, and the data This enables transmission-synchronized transmission in which data is transmitted in synchronization with any transmission cycle required by the next-stage device, regardless of the reception cycle of the device. Since a sampling clock, a shift pulse, or a synchronizing signal is no longer necessary, the circuit becomes simpler, the probability of malfunction due to noise is lowered, and the device is also made smaller. Furthermore, by adopting a data clearing method in the interrupt control means that sequentially erases accumulated data at a set transmission cycle regardless of the presence or absence of a data reception completion signal from the next stage device,
The above data reception completion signal is not necessarily required,
Furthermore, it has become possible to also provide an initialization function that erases false data caused by a noise trigger that occurs when the device is powered on. In addition, when using the data reception completion signal mentioned above, a method is adopted in which accumulated data is cleared in synchronization with the reception completion signal, thereby increasing the speed of data transmission and dealing with variations in reception processing time of the next stage device. became possible. In this way, by adopting the above-mentioned interrupt control means, it becomes easy to deal with all kinds of next-stage receiving devices, and since an initialization function circuit is no longer required, the circuit becomes simpler and the device becomes smaller. is a great thing.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a VTR control system to which a serial data transmitter according to an embodiment of the present invention is applied, Fig. 2 is a block diagram of main parts of the VTR control system, and Figs. VTRC
4 is a block diagram of the transmitter, FIG. 5 is a block diagram of the interrupt control circuit, and FIG. 6 is a circuit diagram of the same. 10...CPU, 20...VTR control device, 46
...ACK signal, 600 ...Transmitter, 8
00... Priority transfer circuit, 810... Primary latch element, 820... Line selection element, 8
30...Second buffer memory, 840...First
Next encoder latch element, 740...Clear data memory, 750...Data clear signal generator,
900... Interrupt controller, 730... Secondary encoder.

Claims (1)

[Claims] 1. a first latch means for temporarily storing a plurality of received data generated from time to time; a first line selection means for giving a first priority to the plurality of received data stored by the first latch means; a second latch means for temporarily storing a plurality of received data preferentially selected by the first line selection means;
The latch means stores a second
clear data storage means for storing received data to be sent to the central processing control unit; and a signal for clearing the received data sent by the clear data storage means to the central processing control unit. data clear signal generating means for generating a data clear signal, and upon receiving an acknowledge signal sent from the central processing control unit, generating an interrupt signal in synchronization with the signal, and controlling the storage means and data clear signal generating means. and an interrupt that transmits data in synchronization with an arbitrary transmission cycle required by the central control unit without depending on the cycle of received data, and transmits data in a self-cycle when the acknowledge signal is not received. A serial data transmitting device comprising a control means.