JPH041375B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel duplex storage device for an information processing device.

In recent years, demands for reliability in computer systems have been increasing, and it is known that various techniques are being adopted to configure systems with high reliability. In particular, the main memory (MEM) is shared by multiple central processing units (CPUs), and if there is a failure in the main memory, the system will go down, so in order to achieve high reliability,
In many cases, methods of parallel multiplexing main storage devices have been proposed for a long time. In the parallel duplex system, main storage devices are connected in parallel to increase the reliability of the entire system. Therefore, in the event that one of the duplexed main storage devices becomes faulty, the faulty device should be recovered from the fault as soon as possible.
It goes without saying that it is desirable to continue parallel operation. However, in the conventional parallel duplication technology for main storage devices, it is relatively troublesome to make the storage contents of two duplexed main storage devices match after recovering a failed device from a failure. Therefore, in conventional duplex main storage devices, this point is not taken into account at all, or even if it is taken into account, a lot of hardware is added to match the above-mentioned storage contents, and the It had lowered its reliability. After all, this usually greatly reduces the effect of increasing reliability through parallel duplication. Furthermore, the conventional technology has the disadvantage that the contents of the two main storage devices cannot be made to match unless the execution of a normal job is temporarily stopped.

An object of the present invention is to match the contents of two parallel duplex main storage devices without affecting the normal operation of the system when recovering from a failure, so that parallel duplex operation can be easily restarted. The object of the present invention is to provide a parallel duplex storage device constructed by adding a small amount of hardware.

In the present invention, access requests from the central processing unit and the like to the parallel duplex storage device are periodically prohibited. In addition, it is possible to set this prohibited time width to two types of time widths, a first time width and a second time width, and when the first time width is set, the parallel duplex storage device is disabled. A refresh request is sent to one or both of the two constituent storage devices within a first time interval. On the other hand, when the second time width is set, the contents of the first of the two storage devices are read out and the contents of the second storage device are refreshed in the first half of the second time width. In the latter half of the second time span, the contents of the first storage device are refreshed and a write request is sent to the second storage device. The data read from the first storage device in the first half of the second time width is used as the write data when this write request is issued. Further, the destination addresses of the same type of operation requests to be sent within the second time period are all fixed to the same address value for both storage devices,
Moreover, these series of operation requests are sent to all addresses of the parallel duplex storage device.

Hereinafter, the parallel duplex storage device according to the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a diagram showing the connection between a parallel duplex storage device and a storage control device forming part of a central processing unit. As shown in FIG. 1a, the first parallel duplex storage device 10 includes the first and second storage devices 1,
2 and a parallel control device 5, which is connected to the first storage control device 20. On the other hand, as shown in FIG. 1b, the third and fourth storage devices 3,
4 are connected to the second storage control device 21, respectively. The third and fourth storage devices 3 and 4 connected to the second storage control device 21 constitute a second parallel duplex storage device 11, which controls data. Parallel control device 5 in FIG. 1a
When considered as being included in the first storage control device 20, it is possible to consider that FIG. 1a is conceptually the same as FIG. 1b. However, the first storage control device 20 has only one port (interface connection port).
The second storage control device 21 is connected to the second parallel duplex storage device 11 through two ports. Therefore, the number of ports per storage control device is smaller in FIG. 1a, which is advantageous in terms of configuration. On the other hand, in FIG. 1a, the first storage control device 2
Since the parallel control device 5 exists between 0 and the first storage device 1 or the second storage device 2, the access time is longer and inferior to that in FIG. 1b.

The present invention is not limited to these configurations, and as described above, FIG. 1a and FIG. 1b can be considered to be conceptually the same. The present invention will be explained using a parallel duplex storage device having the configuration shown in FIG. 1a as an example.

FIG. 2 is a block diagram showing the parallel control device 5 in more detail. In FIG. 2, the parallel control device 5 includes first to fourth buffers 31 to 34 for receiving signals from the first storage control device 20, and fifth to sixth buffers 35 for sending signals. ，
36, the address counter 60, the interrupt control circuit 70, the activation signal generation circuit 90, and the output of the first buffer 31 is the output of the activation signal generation circuit 90.
First OR gate 110 for sending REQ?
, instruction code generation circuit 80 , first to fourth selection circuits 100 , 120 , 45 , 55 , storage device instruction register 130 , and storage device instruction register 1
A fifth selection circuit 150 controlled by 30
, a data register 140 that holds the output of the fifth selection circuit 150, seventh to ninth buffers 41 to 43 for sending signals to the first and second storage devices 1 and 2, and an eleventh buffer. ~13th Batsuhua 51~
53, and tenth and fourteenth storage devices for receiving read data from the first and second storage devices 1 and 2.
It is established from the buffers 44 and 54. The interrupt control circuit 70 controls the lower bits of the address counter 60.
CNT is input, and control signals INT, REF, and STA are sent to a start signal generation circuit 90, an instruction code generation circuit 80,
and first to fourth selection circuits 100, 120,
45, 55, etc. To make the explanation easier to understand, suppose that the second storage device 2 has been disconnected from the system for some reason and only the first storage device 1 is operating normally, and in order to return to parallel duplex operation, the first Assume that it is necessary to transfer the contents of one storage device 1 to a second storage device so that the stored contents of the two storage devices match.

FIG. 3 shows a time chart of some signals in the embodiment shown in FIG. Address counter 60 in FIG. 2 receives a clock signal from an external clock circuit and is constantly counted up, and the upper bit ADD of its output is incremented by 1 every time T shown in FIG. In addition, in Figure 3, the upper bit when the time is 0T
The value of ADD is shown as A. On the other hand, the lower bit CNT of the output of the address counter 60 is input to the interrupt control circuit 70. When the trigger signal TG0 from the external control device is applied to the interrupt control circuit 70 during the period between times 0T and 1T, the time
After 1T, the state of the control signal STA becomes 1, and the first
Data transfer from the storage device 1 to the fifth storage device 2 is started. At the same time, the time interval of state 1 of the control signal INT is expanded from time τ1 to time τ2. As is clear from Fig. 2, the control signal INT is
It is sent to the first storage control device 20 via the sixth buffer 36. When the control signal INT becomes 1, the first storage control device 20 is controlled not to send an operation request until it returns to 0 again. By the control signals REF, STA and the control signal MNO from the storage device instruction register 130,
The instruction code generation circuit 80 generates first and second instruction codes CM1 and CM2. The first instruction code CM1 is used for the first storage device 1, and the second
It is used for the storage device 2 of the instruction code CM2.
The storage device instruction register 130 is a 1-bit register that specifies from which storage device read data is to be sent to the first storage control device 20. Since the first storage device is specified based on the above assumption, 0 is set by the external control device. Since the first and second instruction codes CM1 and CM2 may have any value while the control signal INT is 0, the third
In the diagram, "DON'T CARE" is displayed.
The state of the control signal INT is 1 and the state of the control signal STA
When is 0, a refresh command Ref is sent. On the other hand, when the state of the control signal STA is 1,
Read command in the first half according to the state of control signal MNO
Read and a refresh command Ref is sent in the second half, or a refresh command Ref is sent in the first half and a write command Write is sent in the second half. Now, if the state of the control signal MNO is 0, the first command code CM1 is Read→
Ref, the second instruction code CM2 is Ref→Write. However, if the state of the control signal MNO is 1, the first and second instruction codes CM1 and
The relationship with CM2 is reversed. Start signal generation circuit 9
0 detects the fall of the control signals INT and REF and generates the activation signal REQ. Figure 3 shows the activation signal.
The phase relationship of REQ is also shown. The activation signal generation circuit 90 is constructed using a known conventional technique, and detailed description thereof will be omitted. 1 to 5 in Figure 2
selection circuits 100, 120, 45, 55, 150
Both are two-input type selection circuits, and when each control terminal S becomes state 1, the signal applied to the lower input terminal in FIG. 2 is selected. Therefore, when the state of the control signal INT is 1, as is clear from FIG.
, and the third and fourth selection circuits 45 and 55 select the first and second instruction codes CM1 and CM2 from the instruction code generation circuit 80, respectively. Further, the second selection circuit 120 selects data set in the data register 140.
Since it is assumed that the state of the control signal MNO is 0, the fifth selection circuit 150 selects data from the first storage device via the tenth buffer 44.

As is clear from the above explanation, the control signal
While the state of STA is 0, refresh requests are simultaneously sent from the parallel control device 5 to both the first and second storage devices 1 and 2 at a period T. When the state of the control signal STA is 1, the parallel control device 5
reads data from the first storage device 1 at period T and sets it in the data register 140, and at the same time,
Refresh the second storage device 2. Immediately after that, the first storage device 1 is refreshed and the data in the data register 140 is written into the second storage device 2. That is, the data at the specified address in the first storage device 1 is transferred to the specified address in the second storage device 2, and the data at that address is made to match between the first storage device 1 and the second storage device 2. There is. When this operation is completed for all addresses, the interrupt control circuit 70 operates so that the state of the control signal STA becomes 0 again, and from then on, even if the state of the control signal INT becomes 1, the parallel control circuit 70 5 performs no operation other than refreshing both the first and second storage devices 1 and 2. When the state of the control signal INT is 0, a normal read request or write request is sent from the first storage control device 20. However, the state of the control signal STA is 0
After the change from 1 to 1, writing is always performed to both the first and second storage devices 1 and 2 under control by an external control device. When the state of the control signal INT is 1, data is transferred regardless of the address of the write request in the first storage control device 20, so data transfer from the first storage device 1 to the second storage device 2 is not possible. the first storage controller 2 for addresses that have not been completed;
When writing from 0 is performed, the data at that address match at that point. Therefore, in principle, there is no need to transfer data after that. However, in the present invention, as is clear from the above description, when writing is performed from the first storage control device 20, the first storage device 1 and the second storage device 2 are connected at a certain address. The parallel control device 5 is configured to transfer data from the first storage device 1 to the second storage device 2 for all addresses, regardless of whether the contents match or not. However, it is also possible to configure the parallel control device 5 so as to omit data transfer for addresses whose contents already match. In this case, although the transfer time is shortened, the amount of hardware increases and control becomes complicated, and in some cases, the disadvantages such as higher costs and lower reliability due to the increased amount of hardware may far outweigh the disadvantages. Sometimes it gets bigger.

FIG. 4 shows a specific example of the structure of the instruction code generation circuit 80 shown in FIG. 2. In FIG. In FIG. 4, the control signal STA is input to the sixth and seventh input terminals
The control signal REF and the control signal MNO are input to the control terminals E and the inverter 184 of the selection circuits 185 and 186 of the sixth and seventh selection circuits 18
5,186 selection terminals S0 and S1, respectively. First to third code generation circuits 1
81 to 183 generate refresh codes, read codes, and write codes, respectively, and input terminals A of the sixth and seventh selection circuits 185 and 186.
0 to A3 or the first AND gate 187. The output of the sixth selection circuit 185 is input to the second OR gate 188 and is logically summed with the output of the first AND gate 187. As a result, the obtained logical sum is sent out as the first instruction code CM1. The output of the seventh selection circuit 186 is
OR gate 189 and first AND gate 1
The logical OR with the output of 87 is taken. As a result, the obtained logical sum is sent out as the second instruction code CM2. Next, the sixth and seventh selection circuits 185,1
The signal supplied to the selection terminals S0 and S1 of 86 is
0, S1, the state of the signal appearing at the control terminal E is 1, and S0, S1 are (0, 0), (0,
1), (1,0), and (1,1), the signals input to the input terminals A0, A1, A2, and A3 are selected, respectively. Therefore, when the control signal STA is in the 0 state, the outputs of the sixth and seventh selection circuits 185 and 186 are always in the 0 state. On the other hand, since the first AND gate 187 outputs the input of the first code generation circuit 181 as it is, both the first and second instruction modes CM1 and CM2 become refresh codes. Conversely, the control signal
When the state of STA is 1, as is clear from the above explanation, the first and second instruction codes CM1 and CM2 are set to the fifth instruction code according to the values of the control signals REF and MNO.
It is sent as shown in the diagram. In the instruction code generation circuit shown in detail in Fig. 4, Fig. 2,
It goes without saying that the operation described in FIG. 3 is also possible.

FIG. 6 is a diagram illustrating in detail a specific example of the interrupt control circuit 70 shown in FIG. 2. In FIG. 6, a decoder 71 inputs and decodes the lower bit CNT of the output of the address counter 60 in FIG. As a result of the decoding, state 1 is sequentially output from the output terminals C0 and C1 at predetermined time intervals. The output terminals C0 and C1 of the decoder 71 are the fifth
As shown in the figure, it is connected to the set terminals S of the first and second flip-flops 72, 73, and the output terminal C2 is connected to the reset terminal R and the second to fourth AND gates 171, 172, 173. There is. second and third AND gates 171,
172 each has the output of the third flip-flop 74 and the output of the counter 76 as other inputs, and these gates supply signals to the set terminal S and reset terminal R of the fourth flip-flop 75, respectively. The output terminal Q of the fourth flip-flop 75 is connected to the input terminals of the fourth and sixth gates 173, 175, and is also connected to the reset terminal R of the third flip-flop 74. Furthermore, the output from the output terminal Q of the fourth flip-flop 75 is a control signal.
It is sent externally as STA. One output terminal 0 is connected to the fifth and seventh gates 174 and 176, and also to the clear terminal CL of the interrupt counter 76. Interrupt counter 7
A count-up signal from the fourth AND gate 173 is applied to the count-up terminal CU of 6, and when the count of the interrupt counter 76 reaches a predetermined value, state 1 is output from the output terminal CR. In the initial state, the third and fourth flip-flops 7
Since interrupt counters 4 and 75 are both in the reset state, the interrupt counter 76 is also in the clear state. on the other hand,
The first and second flip-flops 72, 73 are periodically set and reset and provide outputs to the fourth OR gate 177 via the sixth and seventh AND gates 175, 176. When the output of the first flip-flop 72 is set, the pulse width (state 1) of the control signal INT shown in FIG. 3 becomes time .tau.2. On the other hand, as is clear from FIG. 3, the second flip-flop 7
The output of No. 3 is sent out as a control signal REF. However, it goes without saying that the control signal INT is the output of the fourth OR gate 177 and has the same waveform as the control signal REF in the initial state. When the trigger signal TGO is input from an external control device in the initial state, the logical product obtained by the fifth AND gate 174 becomes 1, thereby setting the third flip-flop 74. Therefore, the state of the output of the third flip-flop 74 becomes 1. At this time, when 1 appears at the output terminal C2 of the decoder 71, the state of the output of the second AND gate 171 changes to 1.
Then, the fourth flip-flop 75 is set. As a result, the states of the outputs of the fifth and sixth AND gates 174 and 175 become 0, and the interrupt counter 76 is released from the tally state. When the state of the control signal STA goes to 1, the third flip-flop 74 is reset and the fourth AND gate 173 is opened. Therefore, interrupt counter 7
6 is counted up every time 1 appears at the output terminal C2 of the decoder 71, and the sixth AND gate 17
5 will be held. Therefore, the control signal INT has the same waveform as the output of the first flip-flop 72. When the interrupt counter 76 continues to count up and reaches a predetermined value, that is, a value equal to the number of words of the first and second storage devices in FIG.
1 appears, and the third AND gate 172 opens.
As a result, when 1 appears at the output terminal of decoder 71, fourth flip-flop 75 is reset, the state of control signal STA becomes 0, and interrupt control circuit 7 returns to its initial state.

As is clear from the above description, it goes without saying that the circuit shown in FIG. 6 satisfactorily performs the functions explained in FIGS. 2 and 3. Now, the details of the present invention have been explained above, but according to the present invention, the interrupt time is only slightly increased, and the operation of the central processing unit is not affected at all, and the contents of the second storage device 2 are It is clear that the first storage device 1 can be made to correspond to the first storage device 1. Further, although the amount of hardware increases compared to the case where the present invention is not adopted, these are the first to fourth selection circuits 100, 1 as is clear from FIG.
20, 45, 55, interrupt control circuit 70, instruction code generation times 80, etc., are only a small amount and do not seriously affect the reliability of the system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the configuration of a parallel duplex storage device according to the present invention. FIG. 1a shows the first embodiment, and FIG. 1b shows the second embodiment. FIG. 2 is a detailed block diagram of the embodiment shown in FIG. 1a according to the present invention, and particularly shows a detailed block configuration of the parallel control device. FIG. 3 is a diagram showing a timing diagram of control signals of the parallel control device shown in FIG. 2. FIG. 4 is a block diagram showing details of one embodiment of the configuration of an instruction code generation circuit used in the parallel control device shown in FIG. 2. Fifth
This figure is a diagram showing the relationship between the state of the control signal of the instruction code generation circuit shown in FIG. 4 and the instruction code.
FIG. 6 is a block diagram showing details of one embodiment of the configuration of an interrupt control circuit used in the parallel control device shown in FIG. 2. 1, 2, 3, 4... Storage device, 5... Parallel control device, 10, 11... Parallel duplex storage device, 2
0, 21...Storage control device, 60...Address counter, 70...Interrupt control device, 80...Instruction code generation circuit, 130...Storage device instruction register, 90...Start signal generation circuit, 100, 12
0, 45, 55, 150, 185, 186...Selection circuit, 140...Data register, 31-3
6, 41-44, 51-54...Batsuhua, 11
0,188,189,177...OR gate, 1
87, 171-176...AND gate, 184
...Inverter, 181-183...Code generation circuit, 71...Decoder, 72-75...Flip-flop, 76...Interrupt counter.

Claims (1)

[Claims] 1 first and second storage devices for storing information with the same content at the same address so as to mutually configure a redundant system, and storage devices for the same address of the first and second storage devices; A parallel duplex storage device comprising a parallel control device for controlling writing or reading information of the same content, wherein the parallel control device includes an address counter, an interrupt control circuit, an instruction code generation circuit, a storage device instruction register, a data register, a start signal generation circuit, a plurality of selection circuits,
1, comprising a plurality of buffers and one or more OR gates, and the instruction code generation circuit includes a plurality of code generation circuits, a plurality of selection circuits, and a plurality of OR gates; item or items
The interrupt control circuit includes an AND gate, one or more inverters, and the interrupt control circuit includes a decoder, an interrupt counter, a plurality of flip-flops, a plurality of AND gates, and one or more ORs. a gate, and the interrupt control circuit sends a plurality of control signals to define a first time width and a second time width, and the instruction code generation circuit defines the first time width. A refresh command is sent to the first and second storage devices in response to the above, and a read command is sent to the first storage device and a refresh command is sent in response to the first half of the second time width. The refresh command is sent to the second storage device, and the refresh command is sent to the first storage device and the write command is sent to the second storage device corresponding to the second half of the second time width. A parallel duplex storage device characterized by: