JPH0413886B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a voltage comparison circuit with hysteresis used in a pulsing circuit that converts an analog input signal into a pulse signal.

[Technical background of the invention]

Conventionally, when it is necessary to independently select and set the two threshold voltages (threshold voltage V _TH in the input voltage increasing direction and threshold voltage V _TL in the input voltage decreasing direction) of a voltage comparator circuit with hysteresis, the method shown in Fig. 4 is used. The circuit configuration shown is adopted. That is, the input voltage
V _io is the non-inverting input terminal (+) of the first voltage comparator 51
and the inverting input terminal (-) of the second voltage comparator 52
is applied to A first reference voltage (corresponding to the V _TH described above) is applied to the (-) input terminal of the first voltage comparator 51, and this output terminal is connected to the set input terminal S of the RS type flip-flop FF circuit 53. has been done. Further, a second reference voltage (corresponding to the _VTL ) is applied to the (+) input terminal of the second voltage comparator 52, and this output terminal is connected to the reset input terminal R of the FF circuit 53. has been done.

In the above voltage comparator circuit, as shown in FIG. 5, the output of the first voltage comparator 51 is "1" during a period in which the voltage level of the sine wave input is higher than the V _TH .
During the period when the input voltage level is lower than the _VTL , the output of the second voltage comparator 52 becomes the "1" level. Therefore, the FF circuit 53
is set when the input voltage level becomes greater than the _VTH , and
By being reset when the voltage becomes smaller than _VTL , a pulse voltage as shown appears at the output terminal Q.

[Problems with background technology]

In the conventional circuit described above, there are two voltage comparators,
One FF circuit is used, and these voltage comparators and FF circuits are 7 to 10 in a normal circuit configuration.
Since elements are required, the number of elements in the entire circuit is 21 to 30.
It had the disadvantage of requiring a lot of degree.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
The present invention provides a voltage comparison circuit with hysteresis that can significantly reduce the number of circuit elements used, can independently set the voltages at both ends of the hysteresis width, and can freely set the hysteresis width.

[Summary of the invention]

That is, in the voltage comparison circuit with hysteresis of the present invention, a current mirror circuit is connected as a common load to the first differential pair transistors and the second differential pair transistors, and one transistor of the second differential pair transistors is connected to the current mirror circuit as a common load. an output buffer circuit whose input is the collector potential of the buffer circuit, and a transistor whose base input is supplied with the output potential of the buffer circuit is connected between the emitter interconnection point of the second differential pair transistors and the ground terminal. , the first
The same voltage is applied to the bases of the transistors in each of the differential pair and the second differential pair, and voltages at different levels are applied to the bases of the transistors in the other pair. It is something to do.

Accordingly, by independently applying, for example, the input voltage as the same voltage and the first and second reference voltages as the voltages at different levels, the hysteresis width is determined by these two reference voltages. A voltage comparison operation is performed, the number of circuit elements used is extremely small, and the circuit configuration becomes simple.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, the emitters of a PNP-type first transistor Q ₁ and a second transistor Q ₂ are connected to form a first differential pair, and the emitter connection point and the Vc.c. A first constant current source 1 for flowing a constant current I ₁ is connected between them.
The input voltage _Vio is applied to the base of the first transistor _Q1 , and the second transistor
A first reference voltage V _TH is applied to the base of Q ₂ . Furthermore, the emitters of the PNP-type second transistor Q ₃ and the fourth transistor Q ₄ are connected to each other to form a second differential pair, and between this emitter connection point and the Vc.c. is connected to a second constant current source 2 for flowing a constant current _I2 . and,
The input voltage _Vio is applied to the base of the third transistor _Q3 , and the second reference voltage _VTL is applied to the base of the fourth transistor _Q4 . On the other hand, the bases of the NPN type fifth transistor Q ₅ and the sixth transistor Q ₆ are connected to each other, their respective emitters are grounded, and the collector and base of the fifth transistor Q ₅ are connected to each other. ,
These form a current mirror circuit CM. This current mirror circuit CM serves as a common load for the first differential pair transistors Q ₁ , Q ₂ and the second differential pair transistors Q ₃ , Q ₄ , and serves as a common load for the first differential pair transistors Q 1 , Q 2 and the second differential pair transistors Q 3 , Q 4 . The collector of the transistor _Q5 is connected to each collector of the first transistor _Q1 and the third transistor _Q3 , and the collector of the sixth transistor _Q6 on the secondary side is connected to the second transistor _Q2. and the respective collectors of the fourth transistor _Q4 .
The collector of the transistor _Q4 is connected to an output buffer circuit, for example, the base of a seventh transistor _Q7 of NPN type, and the emitter of this transistor _Q7 is grounded, and between the collector and the Vc.c. power supply. is connected to a third constant current source 3 for flowing a constant current I ₃ , and its collector is connected to an output terminal 4 . Also, this collector has a resistor
_The emitter of this transistor _Q8 is grounded, and the collector is connected to the emitter connection point of the second differential pair transistors _Q3 and _{Q4 .} It is connected.

In the above circuit, the emitter area ratio of transistors Q ₃ and Q ₄ forming the second differential pair is set to 1:n (for example, 1:2), and the constant current source 1 for the first differential pair The ratio of the constant current I ₁ of the constant current source 2 to the constant current I ₂ of the constant current source 2 for the second differential pair is set to 1:n+1 (1:3 in this example), that is, I ₂ =3I ₁ .

Next, the operation when, for example, a sine wave input voltage V _io is applied to the voltage comparison circuit with hysteresis having the above configuration will be described with reference to FIG. 2. During the period A in which the input voltage level is higher than the first reference voltage V _TH , the first differential pair transistors Q ₁ ,
Q ₂ is respectively turned off and on, and a constant current I ₁ flows through the second transistor Q ₂ . Also, when the above-mentioned period A comes, the second differential pair transistor
Q ₃ and Q ₄ remain in the off state during period D, which will be described later. Therefore, when period A begins, no current flows through the primary side transistor _Q5 of the current mirror circuit CM, no current flows through the secondary side transistor _Q6 , and no current flows through the second transistor _Q2. The current I from ₁ causes the seventh transistor
_Q7 is turned on and the output terminal 4 becomes the ground potential (“0” level). As a result, the eighth transistor Q ₈ is turned off, the fourth transistor Q ₄ is turned on, and the second constant current source 2
A constant current I ₂ flows from.

Next, during a period B in which the input voltage level decreases and becomes intermediate between the first reference voltage V _TH and the second reference voltage V _TL , the first differential pair transistor
Q ₁ and Q ₂ are respectively turned on and off, and a constant current I ₁ flows through the first transistor Q ₁ . On the other hand, the second differential pair transistors Q ₃ and Q ₄ remain off and on, respectively, and the transistor Q ₅ on the primary side of the current mirror circuit CM is connected to the first transistor Q 4 . ₁ flows, and _{current I 1 also} flows through the transistor Q ₆ on the secondary side. Therefore, the current I _{2 (} =
3I ₁ ), the seventh transistor Q 7 remains turned on due to the current 2I ₁ other than the current I ₁ flowing to the secondary transistor Q ₆ of the current mirror circuit CM, and thereby the eighth transistor Q ₇ remains turned on. _Q8
remains off.

Furthermore, in a period C in which the input voltage level decreases and becomes smaller than the second reference voltage _VTL ,
The first differential pair transistors Q ₁ , Q ₂ remain respectively in the on and off state, and the transistor Q ₃ in the second differential pair is in the on state, and this third transistor Q ₃ is in the on state. Out of the current I ₂ (=3I ₁ ) from the second constant current source 2, I ₁ flows. Therefore,
Primary side transistor _Q5 of current mirror circuit CM
The current I 1 from the first transistor Q _{1 and} the current I 1 from the third transistor Q ₃ will flow through the secondary transistor Q ₆ , and the current 2 I from the fourth transistor Q ₄ will flow through the secondary transistor Q ₆ . Since the base current necessary for turning on the seventh transistor _Q7 does not flow, the seventh transistor Q7 is turned off, and the output terminal 4 becomes Vc.c. potential ("1" level). This results in constant current I ₃
The eighth transistor _Q8 is turned on,
The current I 2 from the second constant current source ₂ flows through this transistor Q ₈ and the transistor Q 8 is turned on.
Q ₃ and Q ₄ are each turned off. Note that when the above-mentioned period C arrives, currents I ₁ and 2I 1 flow through the third transistor Q ₃ and the fourth transistor Q ₄ in accordance with the emitter area ratio of 1: ₂ , respectively.
Since the respective base-emitter voltages are equal, the accuracy of comparison between the input voltage V _io and the second reference voltage V _TL is good.

Next, during a period D in which the input voltage level rises and becomes intermediate between the second reference voltage V _TL and the first reference voltage V _TH , the second differential pair transistor
Q ₃ and Q ₄ each remain in the off state, and the first
The differential pair transistors Q ₁ and Q ₂ remain in the on and off states. Therefore, the current _I1 from the first transistor _Q1 flows through the primary side transistor _Q5 of the current mirror circuit CM, but no current flows through the secondary side transistor _Q6 , and the current flows through the seventh transistor Q5. Since the base current necessary for turning on transistor ₇ does not flow, it remains in the off state, and the eighth transistor
Q ₈ is driven on by the constant current I ₃ and remains in the on state, and the third and fourth transistors Q ₃ and Q ₄ each remain in the off state.

That is, in the voltage comparison circuit with hysteresis, the first reference voltage V _TH and the second reference voltage
Voltage comparison with a hysteresis width corresponding to the difference from V _TL is possible, and each of the above reference voltages V _TH , V _TL
can be set independently and freely. In addition, in the above circuit, the terminals to which the reference voltages V _TH and V _HL are applied (the second and fourth transistors Q ₂ ,
Since the input impedance of the base of Q ₄ is high,
A reference voltage source with high input impedance can be used, and the voltage range that can be set as the reference voltages V _TH and V _TL is wide. In addition, the first constant current source 1 and the second
By appropriately setting the current ratio with the constant current source 2 and the emitter area ratio of the second differential pair transistors Q ₃ and Q ₄ , the difference between the second reference voltage V _TL and the input voltage V _io can be adjusted. Comparison accuracy improves. Moreover, in the above voltage comparison circuit, if each current source is realized by one transistor, the number of transistors used is 11, the number of resistors used is 1, and the total number of circuit elements used is 12. This is extremely simplified compared to the conventional example.

FIG. 3 shows a modification of the circuit shown in FIG. 1. The differences from the circuit shown in FIG. 1 are (1) resistances R ₂ and R ₃ between the input terminal 5 and the ground terminal; , R ₄ are connected in series, the connection point of resistors R ₂ and R ₃ is connected to the base of the first transistor Q ₁ , and the connection point of resistors R ₃ and R ₄ is connected to the base of the third transistor Q ₃ . (2) The bases of the second transistor Q ₂ and the fourth transistor Q ₄ are commonly connected and the reference voltage V _S is applied thereto; (3) As an output buffer circuit. , connect the base of a ninth NPN transistor Q ₉ to the collector of the seventh transistor Q ₇ , and ground the emitter of this transistor Q ₉ .
The difference is that a fourth constant current source 6 for flowing a constant current _I4 is connected between the collector and the Vc.c. power supply terminal, and the collector is connected to one end of the resistor _R1 . . Since the other parts are the same as in FIG. 1, the same parts as in FIG. 1 are given the same reference numerals.

In the above circuit, the input voltage of input terminal 5
Assuming that transistors Q ₁ and Q ₃ are each turned off during a period in which V _io is higher than the first reference voltage V _TH , the above V _TH is V _TH ×R ₄ /R ₂ +R ₃ +R ₄ =V _S ∴V _TH = R ₂ + R ₃ + R ₄ /R ₄ ×V _S. In addition, the input voltage V _io of input terminal 6
If transistors Q ₁ and Q ₃ are each turned on during a period when V _{TL is smaller than the second reference voltage V TL} , the above V _TL is V _TL ×R ₃ +R ₄ /R ₂ +R ₃ +R ₄ =V _S It is expressed as ∴V _TL = R ₂ + R ₃ + R ₄ /R ₃ + R ₄ ×V _S.

The operation of the circuit shown in FIG. 3 above is carried out in accordance with the operation of the previous embodiment, but by adding the ninth transistor Q ₉ , transistors Q ₇ and Q ₈ are in the same switch state, and the output voltage is The level of V _put has an opposite phase to that of V _put in the above embodiment.

〔Effect of the invention〕

As described above, according to the voltage comparison circuit with hysteresis of the present invention, the number of circuit elements used can be significantly reduced, the voltages at both ends of the hysteresis width can be set independently, and the hysteresis width can be set freely.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the voltage comparison circuit with hysteresis of the present invention, FIG. 2 is a signal waveform diagram shown to explain the operation of the circuit in FIG. 1, and FIG.
4 is a circuit diagram showing another embodiment of the present invention, FIG. 4 is a block diagram showing a conventional voltage comparison circuit with hysteresis, and FIG. 5 is a signal waveform diagram showing the operation of the circuit shown in FIG. 4. 1 to 3, 6...constant current source, 4...output terminal, 5
...Input terminal, Q ₁ to Q ₉ ... Transistor, R ₁ to
R ₄ ...Resistor, CM...Current mirror circuit.

Claims (1)

[Claims] 1. First polarity transistors Q ₁ and Q ₂ whose emitters are connected to each other to form a first differential amplifier pair; and whose emitters are connected to each other to form a second differential amplifier pair; first polarity transistors Q ₃ and Q ₄ whose respective collectors are connected to the respective collectors of the transistors Q ₁ and Q ₂ and whose emitter area ratio is set to 1:n (where n is a positive number); a current mirror circuit CM connected as a load to the collectors of the transistors Q ₃ and Q ₄ ; a first current source 1 that supplies current to the first differential amplifier pair; and a second differential amplifier pair. On the other hand, a second current source 2 supplies a current (n+1) times the current value of the first current source 1, and a base is coupled to the collector of the transistor _Q4 , and the collector is coupled to the output terminal 4. the second
A polarity transistor _Q7 , a third current source 3 that supplies current to the transistor _Q7 , a collector connected to the emitter interconnection point of both the transistors _Q3 and _Q4 , and an emitter connected to a predetermined potential end. a second polarity transistor Q ₈ , and a resistor R ₁ connected between the output terminal 4 and the base of the transistor Q ₈ , the first differential amplifier pair and the second differential amplifier pair; A voltage comparator circuit with hysteresis, characterized in that the same voltage is applied to the bases of each one transistor of a dynamic amplification pair, and voltages of different levels are applied to the bases of each other transistor. . 2. The same voltage is an input voltage, and the voltages at different levels are a first reference voltage VTH and a second reference voltage _VTH .
2. The voltage comparator circuit with hysteresis according to claim 1, wherein the reference voltage _VTL is the reference voltage VTL. 3. The voltage comparator circuit with hysteresis according to claim 1, wherein the same voltage is a reference voltage _VS , and the voltages at different levels are generated by dividing an input voltage. .