JPH0413897Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial field of application] This invention digitally decodes a band-compressed signal, such as a MUSE signal, formed by time axis compression and multiplex sub-sampling processing of a high-definition video signal. , relates to a high-definition video playback device that reproduces and forms a high-definition video signal.

[Prior Art] Conventionally, when transmitting, receiving, recording and reproducing high-definition video signals, it is necessary to narrow the transmission frequency band of the high-definition video signals.
As stated in the preliminary lecture for the foundation commemorative lecture of the NHK Research Institute of Technology and the Broadcast Science Research Institute, published on June 6, 1959, "A new transmission method for high-definition television (MUSE)", time axis compression multiplexing is (TCI) and multiple sub-sampling processing (multiple sub-Nyquist sampling processing) that goes around four fields.
It has been proposed to narrow the transmission frequency band by converting a high-quality video signal into a band-compressed signal using the TCI multiplex sub-Nyquist sample method, that is, a MUSE signal, and then transmitting the signal.

Regarding the MUSE system, which converts high-definition video signals into MUSE signals and transmits them, the MUSE system, which converts high-definition video signals into MUSE signals, is not only published in the above-mentioned "New Transmission System for High-Definition Television (MUSE)," but also published by Denshi Gijutsu Publishing Co., Ltd. on September 1, 1984. From pages 19 to 24 of the September issue (VOL.32) of the magazine “Television Technology” published by Japan Broadcasting Corporation
It is also described in pages 103 to 108 of the April issue of the magazine "Radio Science" published on April 1, 1984.

When a high-definition video signal is converted into a muse signal for television broadcasting, the muse signal formed is converted into a broadcast signal by digital encoding processing of the high-definition video signal, and the broadcast signal is transmitted from the transmitting side to a broadcast signal. It is transmitted to the receiving side via broadcasting satellites, etc.

At this time, the broadcast signal demodulator on the receiving side demodulates the received broadcast signal into a MUSE signal, and the digital decoding processing circuit provided in the high-definition video playback device after the broadcast signal demodulator, that is, the MUSE signal, The demodulated MUSE signal is digitally decoded by the decoder, and the received high-quality video signal is reproduced and formed by the decoding process.

By the way, in order to accurately digitally decode the input MUSE signal, the MUSE decoder has a reproduced clock generation section that is PLL-controlled based on the frame synchronization signal and horizontal synchronization signal in the MUSE signal. , 32.4MHz or double 64.8M in synchronization with the received MUSE signal
A reproduced clock having a reference clock frequency of Hz is generated, and decoding processing including the above-mentioned digital conversion is performed based on the reproduced clock.

The frame synchronization signal is used to lock the frequency of PLL control, and the horizontal synchronization signal is used to set the sampling phase within one clock of the digital conversion clock frequency of 16.2MHz.

By the way, high-definition video signals are not only transmitted and received as in the aforementioned television broadcasting, but are also sometimes recorded and played back using recording media such as video disks and video tapes.
The specification and drawings of the application of No. 2003-12112 describe recording and reproducing high-definition video signals on a video disc.

As described in the specification and drawings of the above-mentioned application, even when recording and reproducing high-definition video signals, the high-definition video signal is converted into a Myuse signal and recorded, and the reproduced Myuse signal is converted into a digital signal. In order to perform decoding processing and reproduce and form a high-quality video signal, the above-mentioned Muse decoder is provided, and the regenerated clock generation section of the decoder generates a regenerated clock in synchronization with the regenerated MUSE signal, and the regenerated clock is used to generate a high-quality video signal. It is necessary to control digital decoding processes such as , digital conversion, and writing, reading, and composition of data formed by digital conversion.

[Problem that the invention seeks to solve]

By the way, the clock generation section of the Muse decoder generates the regenerated clock in synchronization with the received or regenerated MUSE signal, that is, the input band compression signal, as described above.
A recovered clock is generated by PLL control, and in this case, during a no-input period when a band compression signal is not input, for example, no frame synchronization signal or horizontal synchronization signal is input, and the frequency lock of PLL control is largely deviated, causing the recovered clock to frequency will deviate greatly from the reference clock frequency.

Then, when the period of no signal input changes to the period of signal input, and the compressed band signal is input again, the frequency of the reproduced clock has shifted significantly.
It takes time until the frequency of the reproduced clock is locked to the reference clock frequency synchronized with the band compression signal by PLL control, that is, until the PLL lock is applied again. There is a problem that it cannot be done.

[Means for solving problems]

This invention was made keeping in mind the above points, and digitally decodes a band compression signal formed by time axis compression and multiplex sub-sampling processing of a high-definition video signal, and reproduces the high-definition video signal. In the high-definition video reproducing apparatus, the reproduced clock generation section that generates the reproduced clock for the decoding process includes synchronous oscillation control means that performs PLL control on an oscillator for generating the reproduced clock using a synchronization signal of the band compression signal; amplitude detection means for outputting a detection signal with a level proportional to the signal amplitude of the input band compression signal; and comparison means for outputting a no-input detection signal when the level of the detection signal is below a predetermined no-signal detection level. , fixed oscillation control means for outputting a fixed oscillation control signal having a reference clock frequency for the decoding process; and PLL oscillation control from the synchronous oscillation control means to the oscillator during a no-signal input period in which the no-input detection signal is output. The present invention is a high-quality video playback device comprising oscillation control selection means for cutting off a signal and supplying the fixed oscillation control signal to the oscillator.

[Effect]

Therefore, the period during which the band compression signal is input,
That is, during the signal input period when no input detection signal is output, the oscillator generates a regenerated clock in synchronization with the input band compression signal by the PLL oscillation control signal of the synchronous oscillation control means, and the no input detection signal is input. During the no signal input period, PLL control of the oscillator is stopped, and the fixed oscillation control signal of the fixed oscillation control means is supplied to the oscillator, so that the oscillator operates at a fixed frequency based on the fixed oscillation control signal, that is, the reference clock for digital decoding processing. It continues to oscillate at this frequency to generate a regenerated clock.

Since the oscillator continues to oscillate at the reference clock frequency during the period when no signal is input, the next time a band compression signal is input and the oscillator starts to be controlled by the synchronous oscillation control means again using PLL, the frequency lock will be achieved in a short time. As a result, a regenerated clock synchronized with the band compression signal is immediately generated.

〔Example〕

Next, this invention will be explained in detail with reference to drawings showing one embodiment thereof.

Figure 1 shows a Muse decoder of a high-definition video playback device that digitally decodes a MUSE signal to reproduce and form a high-quality video signal. is input via a buffer amplifier 2 to an 8-bit A/D converter 3 and an amplitude detection circuit 4 formed of an absolute value circuit and the like.

The converter 3 uses a recovered clock of 16.2 MHz output from a synchronization separation and recovered clock formation circuit to be described later, that is, a recovered clock of a reference clock frequency for digital decoding processing that matches the subsample phase of the input MUSE signal. The input muse signal is sequentially converted into 8-bit digital video data, and the 8-bit video data is sequentially sent from the converter 3 to the synchronization separation and reproduction clock formation circuit 5, the noise reduction circuit 6, and the motion vector separation circuit 7. is output to.

At this time, the forming circuit 5 extracts the frame synchronization signal and horizontal synchronization signal data of the Muse signal by synchronization separation, and performs PLL control on the internal voltage controlled oscillator using both extracted synchronization signals, and from the oscillator as shown in FIG. A 16.2MHz regenerated clock synchronized with the MUSE signal is supplied to each circuit section.

On the other hand, the reduction circuit 6 receives video data output from the converter 3 as well as video data from two fields before and four fields before, which are read from a second memory (described later). The video data of the current field outputted from the converter 3 and the video data of four fields before are mixed at a constant ratio, and noise in the video data outputted from the converter 3 is reduced.

Furthermore, the reduction circuit 6 is configured so that the current field video data subjected to noise reduction processing and the subsample phase are
The video data of two fields before, which are 180 degrees different, are read out and transferred alternately to the first memory 8 forming the field memory, and at this time, the first memory 8 holds the video data of one field before and three fields before. is read out and transferred to the second memory 9 forming a field memory.

However, the separation circuit 7 separates and extracts the motion vector data in the control signal from the input video data, and outputs the motion vector data to the second memory 9.

The second memory 9 holds the video data of the previous one field and the previous three fields transferred from the first memory 8, and also stores the video data of the previous one field and the previous four fields based on the motion vector data read control. The data is output to the reduction circuit 6 and the motion detection circuit 10.

Therefore, the video data output from the converter 3 is subjected to noise reduction processing by the reduction circuit 6 and held in the first memory 8, and is transferred from the first memory 8 to the second memory 9 after one field. The signal is held in the second memory 9, transferred from the second memory 9 again to the first memory 8 via the reduction circuit 6 after two fields, and transferred to the second memory again after three fields.

That is, one field of video data output from the converter 3 passes through two memories, the first and second memories 8 and 9.

Further, the video data output from the reduction circuit 6 and the video data output from the second memory 9 are input to the still image processing circuit 11, and the processing circuit 11 converts the video data based on the composite data of four consecutive fields of video data. , still areas of the image are subjected to interframe interpolation processing.

Further, the video data output from the reduction circuit 6 is input to the video processing circuit 12, and the processing circuit 12 performs intra-field interpolation on the moving area of the image based on the video data of the current field output from the reduction circuit 6. It is processed.

The still area interpolated video data output from the processing circuit 11 and the moving area interpolated video data output from the processing circuit 12 are input to the mixing circuit 13.

On the other hand, based on the video data output from the converter 3 and the video data output from the reduction circuit 6, the motion detection circuit 10 calculates the difference between the video data of the current field and the video data of one or two frames before. A motion caused by a difference between one or two frames of video data is detected, and detection data for variably setting the mixing ratio of video data in the processing circuits 11 and 12 according to the motion is output to the mixing circuit 13.

Then, the mixing circuit 13 mixes the video data of the processing circuit 11 and the video data of the processing circuit 12 at a mixing ratio based on the detection data of the motion detection circuit 10, and outputs video data obtained by interpolating the still area and the moving area.

Further, the video data output from the mixing circuit 13 is subjected to interpolation of inter-field offset sampling by the field interpolation circuit 14, and then input to the TCI decoder circuit 15, where it is subjected to TCI decoding by the decoder circuit 15. , brightness data, wideband and narrowband color data of a high-quality video signal are reproduced and formed from the input video data.

And the luminance data of the decoder circuit 15 and 2
Three D/A converters 16, 17,
The brightness signal Y, and two types of color signals C _W and C _N of the high-definition video signal are analog-converted by 18 and reproduced by digital decoding processing of the Muse signal.
are output from the converters 16 to 18, respectively.

By the way, the amplitude detection circuit 4, the formation circuit 5, and the comparison circuit described later form a regenerated clock generation section 19, and the detection circuit 4 performs absolute value processing of the input signal to generate a clock signal proportional to the signal amplitude of the Muse signal output from the amplifier 2. The analog detection signal at the voltage level obtained is output to the comparator circuit 20.

Further, the comparison circuit 20 is inputted with the detection signal of the amplitude detection circuit 4 as well as the voltage signal at the no-signal detection level of the reference voltage terminal 21, that is, the reference signal for no-signal detection.

The comparison circuit 20 compares the voltages of the detection signal and the reference signal, and outputs a no-input detection signal of logic 1 (hereinafter referred to as "1") to the formation circuit 5 when the voltage of the detection signal is lower than the voltage of the reference signal. However, when the voltage of the detection signal is higher than the voltage of the reference signal, a logic 0 (hereinafter referred to as "0") input detection signal is output to the forming circuit 5.

That is, the amplitude detection circuit 4 and the comparison circuit 20 form an amplitude detection means and a comparison means, respectively.
The signal amplitude of the input Myuse signal is detected by the detection circuit 4, and the presence or absence of input of the Myuse signal is detected by the comparison circuit 20 based on the detection signal of the detection circuit 4 and the reference signal, During a no-input period when no Muse signal is input, a no-input detection signal of "1" is output from the comparison circuit 20 to the formation circuit 5.

Note that the voltage level of the reference signal, that is, the no-signal detection level is set in advance by an experimental method.

Furthermore, the forming circuit 5 is configured as shown in FIG. The frame synchronization signal data is separated and extracted from the input video data, and the frame synchronization signal of the input muse signal is separated and extracted.

The detector 5b also separates and extracts horizontal synchronizing signal data from the input video data, and separates and extracts the horizontal synchronizing signal of the input Muse signal.

The detector 5a outputs a detected frame pulse to the frame phase difference detector 5c every time a frame synchronization signal is extracted.

Further, based on a regenerated clock output from a voltage controlled oscillator (described later), an internal frame pulse generator 5d generates an internal frame pulse at the timing of a frame synchronization signal with reference to the regenerated clock, and the internal frame pulse is transmitted to a detector 5c. Output to.

Then, the detector 5c detects the phase difference between the detected frame pulse and the internal frame pulse, and outputs data of the phase difference, that is, frame pulse phase difference data, to the cumulative adder 5e. The phase difference data and the output phase difference data are leak-added, and control data for PLL controlling the frequency of the reproduced clock to a frequency based on the frame synchronization signal, that is, PLL frequency control data, is output to the data selection circuit 5f.

Further, the selection circuit 5f selects the frequency control data of the adder 5e based on the input detection signal during the signal input period when the input detection signal of "0" is output from the comparator circuit 20, and selects the frequency control data of the adder 5e. At this time, through analog conversion by the converter 5g, an analog PLL frequency control voltage signal for frequency control of the reproduced clock is output from the converter 5g to the adder 5h.

On the other hand, along with the video data from the converter 3, the detector 5b receives a horizontal synchronizing signal generated by a frequency divider (to be described later), that is, a horizontal synchronizing signal internally generated at the timing of the horizontal synchronizing signal with reference to the reproduced clock. (hereinafter referred to as internal horizontal synchronization signal) is input.

Based on the detection of the phase difference between the separated and extracted horizontal synchronization signal (hereinafter referred to as the detected horizontal synchronization signal) and the input internal horizontal synchronization signal, the detector 5b
The phase difference within each period of the digital conversion clock frequency of the 16.2 MHz converter 5c is detected, and the data of the phase difference, that is, the horizontal synchronization phase difference data, is output to the integrator 5i. Digitally integrates the horizontal synchronization phase difference data generated by the integration, and detects the integrated data generated by the integration, that is, the phase of the reproduced clock.The phase is based on the horizontal synchronization signal.
D/PLL phase control data for PLL control
It is output to the A converter 5j.

Furthermore, the converter 5j converts the input PLL phase control data into analog, and converts the input PLL phase control data into an analog phase control voltage signal for phase control of the regenerated clock.
Output to h.

Then, the adder 5h adds the voltage signals of both converters 5g and 5j, and supplies the oscillation control signal formed by the addition, that is, the PLL oscillation control signal, to the voltage controlled oscillator 5k, and the oscillator 5k receives the input signal.
It oscillates at a frequency and phase set by the voltage of the PLL oscillation control signal, and generates a regenerated clock in synchronization with the muse signal. 5d,
Output to frequency divider 5l.

Note that the frequency divider 5l divides the frequency of the input reproduced clock to generate an internal horizontal synchronization signal, and
The internal horizontal synchronization signal is supplied to the detector 5b.

Therefore, during the signal input period when the comparison circuit 20 outputs the input detection signal, the detectors 5a and 5
c, frequency PLL formed by adder 5e, selection circuit 5f, converter 5g, adder 5h, oscillator 5k, and generator 5d; detector 5b, integrator 5i, converter 5j, adder 5h, oscillator 5k; The oscillation of the oscillator 5k is controlled by the synchronous oscillation control means constituted by the phase PLL formed by the frequency divider 5l, and the oscillator 5k receives the frame synchronous signal of the Muse signal, the horizontal synchronous signal, and the horizontal synchronous signal based on the input PLL oscillation control signal. A regenerated clock is generated in synchronization with the signal, and at this time, the frequency and phase of the regenerated clock follow the input Muse signal and change in the vicinity of the reference clock frequency and reference phase.

Next, during the no-input period when the no-input detection signal of "1" is output from the comparison circuit 20, the selection circuit 5f selects the output data of the fixed data generator 5m instead of the frequency control data of the adder 5e. Select and output to converter 5g.

By the way, fixed frequency control data for controlling the frequency of the reproduced clock to the reference clock frequency is set in advance in the generator 5m, and the generator 5m always outputs the fixed frequency control data to the selection circuit 5f.

Therefore, during the no signal input period, the fixed frequency control data of the generator 5m is input to the converter 5g via the selection circuit 5f, and from the converter 5g to the adder 5h,
An analog frequency control voltage signal formed by analog conversion of fixed frequency control data is output,
A fixed oscillation control signal based on the frequency control voltage signal is supplied from adder 5h to oscillator 5k.

Therefore, during a no-signal input period when no Muse signal is input, that is, during a no-signal input period when the frequency lock of PLL control is largely lost, the selection circuit 5f forming the oscillation control selection means operates to
The PLL oscillation control signal to the oscillator 5k is cut off and the PLL control of the oscillator 5k is stopped, and
Instead of the PLL oscillation control signal, a fixed oscillation control signal based on the fixed frequency control data of the generator 5m is supplied to the oscillator 5k, and at this time, the oscillator 5k
Oscillation is continued at the reference clock frequency based on the fixed oscillation control signal, and a regenerated clock with a fixed frequency approximately at the reference clock frequency is generated. Note that fixed oscillation control means is formed by the generator 5m, the selection circuit 5f, the converter 5g, and the adder 5h.

Since the oscillator 5k oscillates at the reference clock frequency even during periods when no signal is input, the next time the muse signal begins to be input, PLL control is started near the lock frequency of the PLL control, and the frequency lock of the regenerated clock is reached. The time required is shortened, a reproduced clock synchronized with the muse signal is immediately generated and output, and the reproduced clock output from the forming circuit 5 allows accurate decoding processing to be performed at all times.

In addition, in the embodiment, the adder 5e and the generator 5m
A selection circuit 5f is provided between the converter 5g and the converter 5g.
For example, a D/A converter is provided after each of the adder 5e and the generator 5m, and the analog PLL oscillation control signal and fixed oscillation control signal are selectively selected by the selection circuit 5f and output to the adder 5h. Of course, you may do so.

Furthermore, in the above embodiment, the high-definition video signal is converted to a MUSE signal and applied to transmit/receive or record/playback, but the high-definition video signal may be converted to various band compression signals other than the MUSE signal for transmission/reception or recording/playback. Of course, it can be applied when

[Effect of idea]

As described above, according to the high-definition video playback device of this invention, during the signal no-input period when no band compression signal is input, the amplitude detection means detects Outputs a no-input detection signal to the oscillation control selection means,
Based on the control of the oscillation control selection means, the PLL oscillation control signal to the oscillator for generating the recovered clock is cut off, and the PLL control of the oscillator is stopped;
By supplying a fixed oscillation control signal to the oscillator to keep the oscillator oscillating at the reference clock frequency, a band compression signal is input and the oscillator starts again.
When PLL control begins, the frequency lock of the regenerated clock is completed in a remarkably short time, and the regenerated clock immediately begins to be generated in synchronization with the band compression signal, and the band compression signal is always accurately digitally decoded to produce high-definition clocks. It is capable of reproducing and forming video signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the high-quality video reproducing apparatus of this invention, and FIG. 2 is a detailed block diagram of a portion of FIG. 1. 4... Amplitude detection circuit, 5... Synchronization separation and reproduction clock formation circuit, 5a... Frame synchronization signal detector, 5b... Horizontal synchronization signal phase difference detector, 5
c...Frame phase difference detector, 5d...Internal frame pulse generator, 5e...cumulative adder, 5f...
...Data selection circuit, 5g, 5j...D/A converter, 5h...Adder, 5i...Integrator, 5k...
Voltage controlled oscillator, 5l... Frequency divider, 20... Comparison circuit, 21... Reference voltage terminal.

Claims (1)

[Scope of utility model registration request] In a high-definition video playback device that digitally decodes a band compression signal formed by time axis compression and multiplex subsample processing of a high-definition video signal and reproduces and forms the high-definition video signal, a playback clock for the decoding process is generated. The regenerated clock generation section includes a synchronous oscillation control means for PLL controlling the oscillator for generating the regenerated clock using a synchronization signal of the band compression signal, and a detection signal having a level proportional to the signal amplitude of the input band compression signal. an amplitude detecting means for outputting, a comparing means for outputting a no-input detection signal when the level of the detection signal is less than a predetermined no-signal detection level, and a fixed circuit for outputting a fixed oscillation control signal of a reference clock frequency for the decoding process oscillation control means; and an oscillation device that cuts off a PLL oscillation control signal from the synchronous oscillation control means to the oscillator and supplies the fixed oscillation control signal to the oscillator during a no-signal input period in which the no-input detection signal is outputted; A high-definition video playback device comprising control selection means.