JPH0583037B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an input level control circuit for a MUSE decoder.

(b) Conventional technology MUSE as a method for transmitting high-definition video signals
There is a method.

This MUSE method is described in pages 112 to 116 of the magazine "Nikkei Electronics" published by Nikkei McGraw-Hill on March 12, 1984, and
A preliminary lecture collection for the founding commemorative lecture of the NHK Research Institute of Technology and the NHK Broadcasting Science Research Institute on June 6, 2016, “New Transmission Methods for High-Definition Television,” and Nippon Broadcasting Publishing Co., Ltd., published on April 1, 1984. Pages 103 to 108 of the April issue of the magazine "Radio Science" published by the Association, and pages 19 to 10 of the September issue of the magazine "Television Technology" published by Denshi Gijutsu Publishing Co., Ltd., dated September 1, 1984. Details are disclosed on page 24.

In this MUSE method, the encoder on the transmitting side compresses the band of the high-quality video signal using the TCI multiplex sub-sampling method, converts this band-compressed MUSE signal into a broadcast signal, and transmits it, which is received via a broadcasting satellite. The broadcast signal is sent to MUSE by the receiver.
The signal is demodulated and then input to the MUSE decoder, which decodes the compressed band signal, and is decoded and reproduced into the original high-quality video signal.

Furthermore, the MUSE signal can be used as a recording medium such as a video disk or a videotape.
It is conceivable to reproduce high-quality video signals by combining a decoder with a video disk player or VTR. This MUSE decoder is input
A clock synchronized with the horizontal synchronization signal in the MUSE signal performs all signal processing such as A/D conversion of the MUSE signal and storage/readout/synthesis of A/D conversion data, allowing accurate processing of high-quality video signals. It allows decryption.

(c) Problems to be solved by the invention However, this MUSE decoder does not necessarily receive only MUSE signals at appropriate levels;
For example, the level of a reproduced MUSE signal input from a high-definition VTR or a high-definition video disc player is not necessarily at an appropriate level.

If the MUSE signal at the appropriate level is not input to the MUSE decoder and is directly AD converted and digitally processed, the movement of the video is detected based on the level difference of the data between frames at the digital processing stage. Not only will the detection circuit malfunction, but the response of the clock pulse generation circuit that derives clock pulses in response to the phase of the zero-crossing point of the horizontal synchronization signal will also become unstable. Furthermore, the color tone and brightness of the image displayed on the high-definition television receiver also deviate from appropriate conditions.

(d) Means for Solving the Problems Therefore, the present invention provides a method for each of the high level part and low level part of the horizontal synchronizing signal in the MUSE decoder.
An integration circuit that integrates each AD conversion data,
The present invention is characterized by being provided with a subtraction circuit that calculates the difference between each integrated data of the high level part and the low level part, and a variable amplification circuit that controls the amplification gain of the input MUSE signal based on the absolute value of this difference data. .

(E) Effect Therefore, according to the present invention, the input MUSE signal is adjusted so that each average value of the AD conversion data in the low level part and the high level part of the horizontal synchronization signal becomes a predetermined value. Since the amplification gain is determined,
The amplified output level of the MUSE signal is always constant.

(F) Embodiment The present invention will be described below with reference to an illustrative embodiment.

In this embodiment, the present invention is applied to a MUSE decoder that decodes a MUSE signal and forms a high-quality video signal.

First, FIG. 1 shows an overall circuit block diagram of this embodiment. As is clear from this figure, the high quality
The reproduced MUSE signal derived from a VTR etc. is input to the variable amplifier circuit 1 via the input terminal, and then the 8bit
is input to the AD conversion circuit 2. This AD conversion circuit 2 performs AD conversion using a 16.2MHz clock signal that matches the subsample phase.
The converted data is input to a motion vector separation circuit 3 and a synchronization separation circuit 4. A clock signal generation circuit 5 disposed after the synchronization separation circuit 4 has its oscillation frequency determined by the frame synchronization pulse, and its oscillation phase determined by the horizontal synchronization signal.
The clock signal is derived by dividing the 64.8MHz oscillation output. Furthermore, AD conversion data is
The signal is input to the noise reduction circuit 6. This noise reduction circuit 6 is provided with a second memory 7 in accordance with the motion vector data separated by the motion vector separation circuit 3.
The data from 2 fields before and 4 fields before are input, and the noise in the AD conversion data is suppressed by adding the data from 4 fields before and the AD conversion data at a fixed ratio. Therefore, the synthesized video data obtained by this noise reduction is data in which fieldback data two fields before with sub-sampling phases different by 180 degrees and AD converted data with noise suppressed are arranged alternately. This composite video data is first sequentially transferred to the first memory 8. Also, the first memory 8
The data of one field before and three fields before are input in advance to the second memory 7 before new composite video data is transferred. Therefore, the AD conversion data is transferred to the first memory 8 with noise reduced by data from four fields before, transferred to the second memory 7 after one field, and transferred to the first memory 7 according to the motion vector after two fields. Transferred to memory 8, and after 3 fields, transferred to second memory 7
After four fields, the data is read out again according to the motion vector, and the noise in the AD conversion data is suppressed and disappears.

A still image processing circuit 9, which receives the composite data and data from the second memory 7, forms still image data. On the other hand, the video processing circuit 10 that receives only the composite video data forms video data from the noise-reduced AD conversion data. The still image data and moving image data are mixed by a mixer 11, and this mixing ratio is determined by the output of the motion detection circuit 12. This 32MHz mixer data is input to the field interpolation circuit 13 and converted into 64KHz interpolation data. Furthermore, this interpolated data is converted into luminance data and two types of time-extended color data in a TCI decoder, and the two types of color data are synchronized. The synchronized signals are input to first, second, and third DA conversion circuits 15, 16, and 17, respectively, and converted into analog luminance signals Y and color signals CN and CW.

The configuration described above is a well-known configuration as a MUSE decoder, and the gist of this embodiment lies in the following configuration for making the level of the input MUSE signal constant.

The integration circuit 18 that inputs the AD conversion data employs the circuit shown in FIG. 2 to separately integrate the high level part and the low level part of the horizontal synchronizing signal shown in FIG. 3. That is, when the AD conversion data sampled at points a to j shown in FIG.
The converted data and the integrated data of the second latch circuit 25 are added, and the added output is sent to the second latch circuit 2 again.
5 is input to realize integration, and this integration is as follows.
The high level part and the low level part are performed separately and distributed to the third latch circuit 26 and the fourth latch circuit 27, respectively. Therefore, the first and second
The latch circuits 23 and 25 and the adder circuit 24 are inputted immediately before AD conversion data at point a and at point f.
It is reset by a reset pulse just before AD conversion data is input. Further, a common first latch pulse is inputted to the first latch circuit 23 and the second latch circuit 24 from the clock signal generation circuit 5.
Latching of new AD conversion data and latching of addition data are done simultaneously. Further, the clock signal generating circuit 5 sends a second latch pulse and a third latch pulse to the third latch circuit 26 immediately before the AD conversion data of points e and j are added and latched in the second latch circuit 25. and the fourth latch circuit 27
is being input. The integrated data obtained in this way is 10 bits, which is the addition of 4 points of AD conversion data.
This is the data. Therefore, in this embodiment, in order to derive the upper 8 bits of the integrated data as averaged data, the lower
2 bits are truncated. This operation corresponds to averaging AD conversion data.

When this averaged data is input to the subtraction circuit 19 at the next stage, the average difference between the high level portion and the low level portion is determined and difference data is derived. The sign of this difference data is reversed line by line. Therefore, the absolute value conversion circuit 20 converts the sign-inverted difference data into absolute values. This absolute value data includes fluctuations due to noise, etc., and the integration circuit 21 averages the input absolute value data for several lines and converts the integral data with less unnecessary fluctuations into the DA conversion circuit 22 [control signal generation]. circuit]. The output of this DA conversion circuit 22 is input as a gain control signal to the variable amplifier circuit 1, and controls the amplification gain of the MUSE signal. Therefore, the average value of the AD converted data of the low level portion of the horizontal synchronization signal is always specified as 64/256, and the average value of the AD converted data of the high level portion of the horizontal synchronization signal is always specified as 192/256.

In this embodiment described above, the difference between the average values of the high level part and the low level part is converted into an absolute value, and the gain is controlled based on this absolute value.
Although it is possible to keep the MUSE signal at a constant level, it may be difficult to regulate it to a predetermined level. Therefore, if a comparison circuit is provided after the absolute value conversion circuit 20 to detect an increase or decrease in the absolute value data with respect to the reference value (128/256) and control the variable amplifier circuit 1 based on the comparison data, MUSE The signal level can be amplified to a predetermined level.

In addition, in this example, the average value in the high level part and the low level part was obtained, but for example, as shown in FIG. If a register 30 is provided and the AD converted data at point C in FIG. 3 is derived from the shift register 30 at the timing when the AD converted data at point g in FIG. You can.
In order to convert the subtracted data in FIG. 4 into an absolute value, it is input to the exclusive OR circuit 31 along with the inverted output of the carry output due to the subtraction, and this exclusive OR data and the inverted output of the carry output are input to the adder circuit 32. It is configured so that the values are added at the same time.

(G) Effects of the Invention Therefore, according to the present invention, an accurate high-quality video signal can be formed for decoding while keeping the MUSE signal at an appropriate level, and the effect is great.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram showing one embodiment of the present invention, Fig. 2 is a circuit block diagram of the same main part, Fig. 3 is a diagram explaining signal waveforms, and Fig. 4 is a main part circuit block diagram according to another embodiment. Figures are shown respectively. 1...Variable amplifier circuit, 2...AD conversion circuit, 18...
Integration circuit, 19...subtraction circuit.

Claims (1)

[Claims] 1. In a MUSE decoder that inputs a MUSE signal obtained by band-compressing a high-quality video signal using the TCI multiplex subsampling method and decodes the MUSE signal to form a high-quality video signal, A variable amplifier circuit that receives the MUSE signal as a signal input, an AD conversion circuit that performs AD conversion on the MUSE signal and derives AD conversion data, and inputs each AD conversion data of the low level part and high level part of the horizontal synchronization signal. an integration circuit that derives each integrated data based on the absolute value of the difference data; a subtraction circuit that receives the integrated data of the low level portion and high level portion of the horizontal synchronization signal and derives the difference data; A high-quality video signal level control circuit comprising a control signal generation circuit that supplies a gain control signal to a variable amplifier circuit.