JPH0535635B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a clock control circuit for stably deriving a high-quality still image video signal from a band compression decoder.

(b) Conventional technology MUSE as a method for transmitting high-definition video signals
There is a method. Regarding this MUSE method, 1984
Pages 112 to 116 of the magazine "Nikkei Electronics" published by Nikkei McGraw-Hill on March 12, 1982, and the preliminary lecture collection of the foundation commemorative lecture "New Transmission Method for High-Definition Television" dated June 6, 1980. and pages 19 to 24 of the September issue of the magazine “Television Technology” published by Denshi Gijutsu Publishing Co., Ltd., and pages 103 to 108 of the April issue of the magazine “Radio Science” published by the Japan Broadcasting Publishing Association. ing. In this MUSE method, a high-quality video signal is band-compressed using the TIC multiplex sub-sampling method at the decoder on the transmitting side, and the MUSE
The signal is converted into a broadcast signal and transmitted, and the broadcast signal received through the broadcast satellite is processed by the receiver.
It is converted to a MUSE signal, input to a band compression decoder, and converted to the original high-definition video signal. This band compression decoder uses a clock synchronized with the horizontal synchronization signal in the input MUSE signal.
It performs all signal processing such as AD conversion of MUSE signals and storage/reading/synthesis of AD conversion data, making it possible to reliably synthesize high-quality video signals.

The band compression decoder stores AD conversion data for four fields in order to synthesize a high-quality video signal, and it becomes possible to synthesize a high-quality still image video signal using only this stored data. Therefore, the applicant previously filed Japanese Patent Application No. 59-47767.
We have proposed a configuration that derives a high-quality still image video signal by cyclically reading data stored in a memory and composing the read data.

(c) Problems to be solved by the invention However, 32.4 MHz or 2 MHz is used in a band compression decoder to synthesize high-quality video signals.
The double clock is derived from a PLL circuit that uses the horizontal synchronization signal in the MUSE signal as a reference signal, so
In the conventional example described above, even when synthesizing high-quality still image video signals, the information is input regardless of playback information.
The clock will be synchronized with the horizontal synchronization signal in the MUSE signal. Therefore, especially when the MUSE signal is derived from a high-definition video disk player as in the conventional example described above, the high-definition still image video signal is not correctly synthesized as a result of the clock being synchronized with the unstable horizontal synchronization signal. In some cases, if the reproduced information is interrupted, it becomes difficult to generate the clock itself. Furthermore, even if the MUSE signal is a broadcast signal, if the horizontal synchronization separation circuit malfunctions due to noise or the horizontal synchronization signal becomes discontinuous due to channel switching on the receiver during still image playback, the clock will It may be disturbed.

Therefore, no matter which MUSE signal is input, if the clock is synchronized with the horizontal synchronization signal of the MUSE signal, which is not directly related to the playback information, during still image playback, a stable high-quality still image video signal can be obtained. is not obtained.

(d) Means for solving the problem Therefore, the present invention is characterized in that the oscillation control output input to the oscillation circuit that generates the clock is fixed.

(E) Effect Therefore, according to the present invention, during normal operation, the clock synchronized with the input MUSE signal synthesizes high-quality video signals, and during still image playback, the constant clock synthesizes high-quality still image video signals. I will do it.

(F) Embodiment The present invention will be described below with reference to an illustrative embodiment.

In this embodiment, the present invention is applied to a high-definition still image playback circuit that also enables still image playback by inputting a playback MUSE signal from a high-definition video disk player to a band compression decoder that has a built-in broadcast signal receiver. It is something to do.

FIG. 1 shows a main circuit block diagram of this embodiment. The basic configuration of this circuit block diagram is almost the same as the configuration shown on page 116 of Nikkei Electronics mentioned above.

As is clear from this figure, the broadcast signal received by antenna 1 is received by receiving circuit 2 and demodulated into a MUSE signal. On the other hand, the reproduction MUSE signal of the video disc player is inputted via an external input terminal. Both MUSE signals are selected by selection switch 3. In this embodiment, a case will be explained in which a reproduction MUSE signal of a high-definition video disk player is selected as an example.

The selected MUSE signal is input to an 8-bit AD conversion circuit 4, and AD conversion data is sequentially derived at 16.2MHz matching the sub-sample phase based on the clock signal.

This AD conversion data is input to the motion vector separation circuit 5, and the motion vector in the control signal is separated. The AD conversion data is also input to the frame pulse separation circuit 6 and the horizontal synchronization pulse generation circuit 7, and a frame synchronization pulse of the frame period and a horizontal synchronization pulse of the horizontal synchronization period are derived.

This horizontal synchronizing pulse contains a jitter component in the reproduced MUSE signal, and also serves as a reference input to the oscillation circuit 9 that generates the clock. That is,
The 64.8 MHz clock is converted into a divided output of the horizontal synchronization period in the frequency divider circuit 10 and fed back, and the phase is compared with the horizontal synchronization pulse in the phase comparator circuit 11. This phase comparison data is input to the next stage data latch circuit (hold circuit) 12, and is latched (held) by the horizontal synchronizing pulse. This latch data is input to the subsequent DA conversion circuit 13, and the DA conversion output is used as the control input of the oscillation circuit 9. Therefore, the 64.8 MHz oscillation output (clock) fluctuates following the jitter in the reproduced MUSE signal, and subsequent data processing is performed in accordance with the jitter. In addition to 64.8MHz, the clock used for data processing is 32.4MHz and 16.2MHz.
is also required. Therefore, in this embodiment, the oscillation output is frequency-divided by first and second flip-flops 14 and 15.

Furthermore, the MUSE signal is time-division multiplexed by converting audio data into PCM during the vertical blanking period.
Therefore, the audio processing circuit 8 that inputs the AD conversion data selects only the PCM audio data during the vertical blanking period and decodes the original two-channel audio signal.

The video information in the AD converted data is input to the noise reduction circuit 16. This noise reduction circuit 16
inputs the data from 2 fields before and the data from 4 fields before, which are read from the second memory in accordance with the motion vector, and by adding the data from 4 fields before and the AD conversion data at a fixed ratio. Reduces noise in AD conversion data. Therefore, from this noise reduction circuit 16, the fieldback data of two fields before with the sub-sampling phase different by 180 degrees and the noise-reduced data are obtained.
AD conversion data are derived alternately. In the steady state, the first flip-flop 24 uses the frame synchronization pulse as a clock input, the high-level output as a data input, and uses the high-level flip-flop output as a control input for the noise reduction circuit 16. Therefore, the noise reduction circuit 1
6 receives a high level control input to reduce noise, and receives a low level control input to block AD conversion data and allow feedback data to pass.

The composite data synthesized in the noise reduction circuit 16 is sent to the first memory 1 constituting the field memory.
7, and the data one field before and the data three fields before in the first memory 17 are transferred to the second memory 18 constituting the field memory. Therefore, the AD conversion data is transferred to the first memory 17 with noise reduced, transferred to the second memory 18 after one field, transferred to the first memory 17 via the noise reduction circuit 16 after two fields, and transferred to the first memory 17 through the noise reduction circuit 16 after two fields. After the field, it will be transferred to the second memory. That is, AD conversion data circulates twice in both memories.

On the other hand, the interframe interpolation circuit 19 uses the synthesized data transmitted at a period equivalent to 32.4 MHz and the first memory 17.
and the read data of 64.8 MHz to synthesize still image data with a period equivalent to 64.8 MHz.

Further, the intra-field interpolation circuit 19 synthesizes 64.8 MHz moving image data from only the synthesized data.

The mixer 22 that inputs still image data and moving image data includes a motion detection circuit 21 that detects motion due to a one frame difference or two frame difference by comparing AD conversion data with data one frame or two frames before. Both data are mixed at a mixing ratio determined by the output.

This mixer output is input to the TIC decoder 23 to derive the original high-quality video signal.

The above-mentioned signal processing is performed in synchronization with the above-mentioned clock, and since the operation of the signal processing is a well-known technique disclosed in the above-mentioned conventional example, further detailed explanation will be omitted. do.

In this embodiment, still images are played back when the still image switch SW is closed. That is, when the still image switch SW is closed, the first flip-flop 24
The data input of becomes low level, AND circuit 2
The passage of the horizontal synchronization pulse that had passed through the signal line 5 is blocked.

Therefore, the data latch circuit 12 is a still image switch.
A new latch is interrupted at the same time as the SW is closed. Therefore, the DA conversion circuit 13 fixes the oscillation frequency of the oscillation circuit 19 by continuing to DA convert the last latch data while the still image switch SW is closed.

On the other hand, the first flip-flop 6 to which low-level data is input receives a low-level control input and a noise reduction circuit 1 in synchronization with the input of the frame synchronization pulse.
Enter 6. Therefore, immediately after the frame synchronization pulse is generated, the noise reduction circuit 16 blocks the AD conversion data and feeds back the read data of the second memory 18 as it is to the first memory 17, so that both memories 1
The data in 7 and 18 are circulated by a fixed clock to continue to stably derive a high quality still image video signal from the TCI decoder 23. In the above embodiment, the operation of the data latch circuit is interrupted in conjunction with the closing of the still image switch SW.
It goes without saying that if the latch operation is interrupted based on the first flip-flop output, similar to the noise reduction circuit 16, AD converted data can be stored more accurately.

(G) Effects of the Invention Therefore, according to the present invention, data is read out and processed using a stable clock during still image reproduction, so that stable still image reproduction is possible and the effect is great.

[Brief explanation of the drawing]

The figure is a circuit diagram and block diagram showing one embodiment of the present invention. SW... Still image switch, 9... Oscillator circuit.

Claims (1)

[Claims] 1. Inputting a MUSE signal obtained by band-reducing a high-quality video signal using the TCI multiple subsampling method,
An oscillation circuit that generates a block is controlled by an oscillation control output that follows a synchronization signal in the MUSE signal, and the MUSE signal is AD converted in synchronization with the clock, and the AD conversion data is synchronized with the clock. While storing data in the memory for 4 fields, the data read out from the memory synchronized with the clock during normal operation and the AD conversion data are combined to derive a high-quality video signal, and the storage in the memory is interrupted when playing still images. In the band compression decoder, the data in the memory is read out cyclically in synchronization with the clock, and the read data is synthesized to derive a high-quality still image video signal. A clock control circuit for a high-quality still image reproduction circuit characterized by providing a hold circuit for fixing the output.