JPH04142073A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04142073A
JPH04142073A JP2264205A JP26420590A JPH04142073A JP H04142073 A JPH04142073 A JP H04142073A JP 2264205 A JP2264205 A JP 2264205A JP 26420590 A JP26420590 A JP 26420590A JP H04142073 A JPH04142073 A JP H04142073A
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
chips
electric circuit
minimize
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2264205A
Other languages
Japanese (ja)
Inventor
Makoto Takahashi
誠 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP2264205A priority Critical patent/JPH04142073A/en
Publication of JPH04142073A publication Critical patent/JPH04142073A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To minimize a package area by constituting an electric circuit with a plurality of semiconductor chips laminated in several stages. CONSTITUTION:A chip 1 (2) is mounted on an island 4 by means of a bonding agent. A chip 2(3) is further mounted thereon in a similar manner as the chip 1. The chip 1, the chip 2, and the inner lead 1 can be interconnected with a bonding wire or the chip 1 and the chip 2 can be interconnected with the bonding wire as well. It is possible to inhibit the horizontal expansion and minimize the package area, even if the number of chips increased, by constituting an electric circuit laminated in several stages in a semiconductor device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体装置の構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a semiconductor device.

〔従来の技術〕[Conventional technology]

従来の半導体装置は、半導体チップ固定用アイランドの
平面上に、一つ又は複数個のチップを平面的に配置し、
電気回路を構成している。In a conventional semiconductor device, one or more chips are arranged in a plane on a plane of a semiconductor chip fixing island,
It constitutes an electric circuit.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置はチップ固定用アイランドの上に一つ
又は複数個のチップを平面的に配置し、電気回路を構成
しているか、チップサイズあるいはチップ個数の増大に
より実装面積か増大するという問題点がある。Conventional semiconductor devices have one or more chips placed on a chip fixing island to form an electrical circuit, or the problem is that the mounting area increases as the chip size or number of chips increases. There is.

本発明の目的は、従来の欠点を除去し、実装面積を極小
にすることができる半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that eliminates the conventional drawbacks and can minimize the mounting area.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、複数の半導体チップを複数段に
重ねて電気的回路を構成することを特徴としている。従
ってチップ個数が増えても、横方向の拡大が抑えられ、
実装面積を極小にする事ができる。The semiconductor device of the present invention is characterized in that a plurality of semiconductor chips are stacked in multiple stages to form an electrical circuit. Therefore, even if the number of chips increases, lateral expansion is suppressed,
The mounting area can be minimized.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）、（ｂ）は、本発明の半導体装置の上面図
及び側面図である。アイランド４の上に接着剤を用いて
チップ１をマウントし、その上に絶縁物を介して、チッ
プ２をチップ１同様マウントする。チップ１．チップ２
及びインナーリード間又はチップ１とチップ２をボンデ
ィングワイヤーにて結線することにより実施例を構成す
ることがてきる。FIGS. 1(a) and 1(b) are a top view and a side view of a semiconductor device of the present invention. Chip 1 is mounted on island 4 using an adhesive, and chip 2 is mounted thereon in the same manner as chip 1 via an insulator. Chip 1. Chip 2
The embodiment can be constructed by connecting the inner leads or the chip 1 and the chip 2 with a bonding wire.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体装置において、チ
ップを数段重ね電気回路を構成しているので、チップ個
数が増しても横方向の拡大が抑えられ実装面積を極小に
できるという効果を有する。As explained above, the present invention has the effect that in a semiconductor device, chips are stacked in several stages to form an electric circuit, so even if the number of chips increases, lateral expansion can be suppressed and the mounting area can be minimized. .

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、（ｂ）は本発明の一実施例の上面図及び
側面図である。 １・・・インナーリード、２・・・チップ１．３・・・
チップ２．４・・・アイランド、５・・・ボンディング
ワイヤー、６・・・絶縁物。FIGS. 1(a) and 1(b) are a top view and a side view of an embodiment of the present invention. 1... Inner lead, 2... Chip 1.3...
Chip 2.4...Island, 5...Bonding wire, 6...Insulator.

Claims (1)

【特許請求の範囲】[Claims] 　半導体チップを複数段重ねて電気回路を構成すること
を特徴とする半導体装置。A semiconductor device characterized by configuring an electric circuit by stacking multiple semiconductor chips.
JP2264205A 1990-10-02 1990-10-02 Semiconductor device Pending JPH04142073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2264205A JPH04142073A (en) 1990-10-02 1990-10-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2264205A JPH04142073A (en) 1990-10-02 1990-10-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04142073A true JPH04142073A (en) 1992-05-15

Family

ID=17399949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2264205A Pending JPH04142073A (en) 1990-10-02 1990-10-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04142073A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100235108B1 (en) * 1993-03-19 1999-12-15 윤종용 Semiconductor package
EP1094517A3 (en) * 1999-10-19 2002-04-10 Fujitsu Limited Semiconductor device and method for producing the same
WO2002084737A3 (en) * 2001-04-10 2003-07-03 Microchip Tech Inc Arrangement and method of arrangement of stacked dice in an integrated electronic device
US8134240B2 (en) 2006-07-27 2012-03-13 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method for the same
CN105810670A (en) * 2014-12-31 2016-07-27 北京兆易创新科技股份有限公司 Memory chip stacked packaging device and method
JP2018093212A (en) * 2018-01-10 2018-06-14 ラピスセミコンダクタ株式会社 Semiconductor device and measurement apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100235108B1 (en) * 1993-03-19 1999-12-15 윤종용 Semiconductor package
EP1094517A3 (en) * 1999-10-19 2002-04-10 Fujitsu Limited Semiconductor device and method for producing the same
EP1713122A3 (en) * 1999-10-19 2006-11-02 Fujitsu Limited Semiconductor device and method for producing the same
WO2002084737A3 (en) * 2001-04-10 2003-07-03 Microchip Tech Inc Arrangement and method of arrangement of stacked dice in an integrated electronic device
US8134240B2 (en) 2006-07-27 2012-03-13 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method for the same
CN105810670A (en) * 2014-12-31 2016-07-27 北京兆易创新科技股份有限公司 Memory chip stacked packaging device and method
JP2018093212A (en) * 2018-01-10 2018-06-14 ラピスセミコンダクタ株式会社 Semiconductor device and measurement apparatus

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