JPH04143992A - Address generation circuit for image memory - Google Patents

Abstract

PURPOSE:To easily generate an address by setting N bits from low-order first to N-th bits of a first address counter as the low-order bits of a column address, and setting the N bits from low-order (N+1)-th to 2N-th bits as the low-order bits of a row address. CONSTITUTION:Address counters 11 and 12 are operated by a common clock C, and the row address Ar1 is comprised setting the output of the fourth bit, the fifth bit, and the sixth fit from the lower-order of the counter 11 in this case as low-order three bits, and also, the column address Ac1 is comprised setting the output of the first bit, the second bit, and the third bit from the low-order of the counter 11 as the low-order three bits. Thereby, the row address Ar1 progresses by one at every eight progression of the column address Ac1, and the address making access sequentially in each block unit of 8X8 word can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address generation circuit for an image memory, and more particularly to an address generation circuit for an image memory used in a circuit that encodes and decodes image data in units of blocks.

[Conventional technology]

As shown in FIG. 3, a conventional image memory address generation circuit includes a column address counter 21, a row address counter 22, and a selector 23 for switching between a column address and a row address. The column address counter 21 generates and outputs a column address Ac in response to a column start address Be and a clock Cc having the same cycle as data reading and writing. The row address counter 22 selects the row address A according to the row start address Br and the clock Cr applied every 10 data accesses.
Generate and output r. The selector 23 selects a column address Ac and a row address Ar according to a selection signal S and outputs the selected address as an address AO.

[Problem to be solved by the invention]

When encoding and decoding image data in blocks,
For example, when processing in blocks of 8 x 8 words,
It is necessary to access the image memory as shown in FIG. In order to generate addresses accessed in blocks as shown in FIG. 2 using the conventional image memory address generation circuit described above, a complicated control circuit is required.

An object of the present invention is to provide an image memory address generation circuit that can generate addresses for accessing the image memory in blocks with a simple circuit configuration.

[Means to solve the problem]

The address generation circuit of the image memory of the present invention is 2NX2N
(N is an integer of N>2) In the address generation circuit of the image memory that generates column addresses and row addresses for accessing image data for each block divided into words, a counting operation is performed in accordance with a common clock.
It includes first and second address counters that output signals of bits (M is an integer where M>N), and the N bits from the first lower bit to the Nth bit of the first address counter are provided.
bits are the lower bits of the column address, and the lower N11th bit of the first address counter to the second
N bits up to the Nth bit are configured as lower bits of the row address, and means for adding a column start address and a row start address to the column address and the row address, respectively, and the first and second additions. The device may be configured to include means for comparing the address output by the circuit with the column end address and the row end address, respectively, and stopping the first and second address counters when they match.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
This figure shows a configuration for generating addresses to be accessed in blocks of 8×8 words on an image memory having an address space of 12×512 words.

The address counters 11 and 12 operate on a common clock C, and the outputs of the fourth, fifth, and sixth bits from the lowest order of the address counter 11 constitute the row address Art as the lowest three bits. 1st bit, 2nd bit, and 3rd bit from the bottom of counter 11
Column address A with the bit-th output as the lower 3 bits
Configure ct. By doing this, the row address Arl is changed to the column address Ac as shown in FIG.
Each time l advances by 8, it advances by 1, and addresses can be generated to sequentially access each block of 8×8 words.

In addition, column address AC1 is added to adder circuits 13 and 14.
and start addresses BC and B to row address Arl.
By adding r to each, it becomes possible to start accessing from any address in the image memory. Furthermore, the comparison circuits 15 and 16 compare the end addresses Ec and Er with the column address Ac2 and row address Ar2 output from the addition circuits 13 and 14, and when they match, the logic circuits 18 and 19 generate an enable signal. It is also possible to stop the operation of each address counter 11, 12 by doing so. The selector 17 selects the column address Ac2 and the row address Ar2 according to the selection signal S and outputs the selected column address Ac2 and the row address Ar2 as the address Ao.

In this embodiment, a case has been described in which addresses are generated to be accessed in blocks of 8 x 8 words on an image memory having an address space of 512 x 512 words, but 2N x 2N (N is an integer where N>2) Addresses for accessing image data can be similarly generated for each block divided into words.

〔Effect of the invention〕

As explained above, according to the present invention, 2N × 2N (
(N is an integer with N>2) When generating buttress and row addresses divided into words, count operations are performed according to a common clock and M pis) (M is an integer of MAH)
A first and a second address counter are provided which output a signal, and N bits from the first lower bit to the Nth bit of the first address counter are used as the lower bits of the column address, and the first address counter outputs a signal of the column address. An address can be easily generated by using N bits from the N11st bit to the 2nd Nth bit of the lower column of the counter as the lower bits of the row address. Further, by using an address obtained by adding a column start address and a row start address to a column address and a row address, respectively, access can be started from an arbitrary address. Furthermore, by comparing the column address and row address with the column end address and row end address, and stopping the first and second address counters when they match, it is possible to stop the first and second address counters at any address.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
aL(b) is a diagram showing the movement of column address Acl and row address Arl shown in FIG. 1, and FIG. 3 is a block diagram showing an example of an address generation circuit of a conventional image memory. 11.12...Address counter, 13.14
... Addition circuit, 15.16 ... Comparison circuit, 17゜23 ... Selector, 18.19 ...
...Logic circuit, 21 ... Column address counter, 22 ... Row address counter N A
cl, Ac2+ Ac... Column address,
Arl, Ar2+ Ar...Row address,
Be... Column start address, Br...
・Row start address, C, Cc, Cr...Clock, EC...Column end address, Er...
...Row end address S...Selection signal.

Claims (1)

[Claims] Image memory address generation that generates column addresses and row addresses for accessing image data for each block divided into 1, 2^N x 2^N (N is an integer where N>2) words. In the circuit, the first and second circuits perform a counting operation according to a common clock and output an M-bit signal (M is an integer where M>N).
N bits from the first lower bit to the Nth bit of the first address counter are the lower bits of the column address, and the lower bits from the N+1st lower bit of the first address counter An address generation circuit for an image memory, characterized in that N bits up to the 2Nth bit are used as lower bits of the row address. 2. The address generation circuit for an image memory according to claim 1, further comprising means for adding a column start address and a row start address to the column address and the row address, respectively, and addresses output by the first and second addition circuits. and a column end address and a row end address, and means for respectively stopping the first and second address counters when they match.