JPH0414497B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an integrated circuit including a P-channel transistor.

Integrated circuits containing N-channel transistors use Linderash technology, which has greatly improved yield and reliability. This is because when a contact hole is just opened, a sharp corner is formed in the contact hole of the phosphor glass film of the surface insulating film, so if Al is vapor-deposited on this surface and patterned for wiring, the Al Since wire breakage is likely to occur, in order to avoid this, high-temperature heat treatment is applied to make the corners gentle to prevent wire breakage. This method is called Lindarashi. However, when this phosphorus is applied to an integrated circuit including a P-channel transistor, phosphorus is ejected from the phosphorus glass film during heat treatment, and out-diffuses into the source and drain regions of the P-channel transistor through the contact hole, resulting in N on the surface of the region. form a mold layer,
A PN junction occurs. Therefore, even if the source and drain electrodes are formed by vapor depositing Al, a PN junction will be present between these electrodes and the source and drain regions, making ohmic contact impossible. Figure 1 is a diagram explaining this, where 10 is an N-type silicon semiconductor substrate, 1 and 2 are source and drain regions.
P ⁺ type diffusion layer, 3 is field and gate insulating film,
4 is a polycrystalline silicon film serving as a gate electrode, and 5 is a phosphorus glass film deposited by chemical vapor deposition (CVD) or the like. Reference numerals 6 and 7 designate phosphorus, that is, phosphorus jumps out from the phosphorus glass film 5 during the softening treatment of the phosphorus glass film, enters the source and drain regions 1 and 2, and is an N ⁺ diffusion layer formed near the exposed surface thereof. This N ⁺ diffusion layer has the same conductivity type as the source and drain regions in an N-channel transistor, so there is no problem, but in a P-channel transistor, a PN junction is formed in the source and drain regions, and the Al electrode is connected to the source and drain regions. This causes contact failure and becomes a big problem.

The present invention has been made to improve this problem, and forms a thin non-doped CVD film or a thin thermal oxide film on the exposed surface portions of the source and drain regions to prevent N ⁺ diffusion formation.

Next, this will be explained in detail with reference to examples.

FIG. 2 shows an embodiment of the invention. In the figure 1
0 is an N-type silicon semiconductor substrate, 1 and 2 are sources,
A P ⁺ type diffusion region forming a drain region, 3 a field and gate insulating film, 4 a polycrystalline silicon gate electrode, and 5 a phosphorus glass film. The method of forming these regions and films is the same as before. Contact holes are made in the phosphorus glass film deposited on the surface, and thin non-doped CVD films are deposited on the exposed surfaces of the source and drain regions 1 and 2 by chemical vapor deposition (chemical vapor deposition). CVD) or a thin thermal oxide film is formed by low-temperature oxidation method8,9
will be established. In this way, the non-doped CVD film or the thermal oxide film 8, 9 becomes a barrier against out-diffusion of phosphorus, and phosphorus in the phosphorus glass film flows from the contact hole to the source and drain regions 1, 2.
can prevent it from spreading.

The non-doped CVD film and thermal oxide films 8 and 9 produced here are removed by etching with a hydrofluoric acid solution before the next electrode wiring deposition, so as not to interfere with the contact. As described in detail above, according to the present invention, by covering the exposed surfaces of the source and drain regions in a semiconductor device such as a transistor including a P-channel transistor with a thin oxide film, phosphorus from the phosphorus glass film generated during lindrision is removed. It is possible to prevent out-of-day fading and improve the manufacturing yield and reliability of semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a P-channel transistor at a stage where linear lashing has been performed, and FIG. 2 is a cross-sectional view illustrating an embodiment of the present invention. In the figure, 1, 2...P ⁺ type source, drain region, 3...insulating film, 4...gate electrode, 5
...phosphorus glass film, 6,7...N ⁺ diffusion layer, 8,
9...Non-doped CVD film or thermal oxide film, 10...
...It is a silicon semiconductor substrate.

Claims (1)

[Claims] 1. A contact hole reaching the impurity region is formed in a phosphorus glass film deposited on a silicon semiconductor substrate having a P-type impurity region, and then heat treatment is performed to close the contact hole in the phosphorus glass film. In the method for manufacturing a semiconductor device, the method includes a step of smoothing out a steep corner formed in a portion or other portion, after the contact hole is formed, phosphorus is removed from the phosphorus glass film into the P-type impurity region during the heat treatment. A semiconductor characterized in that the heat treatment is performed after an oxide film layer for preventing diffusion is provided on the exposed surface portion of the P-type impurity region in the contact hole, and then the oxide film layer is removed. Method of manufacturing the device. 2 Oxide film layer is non-doped by chemical vapor deposition
2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is a CVD layer or a thermal oxide film layer formed by low-temperature oxidation.