JPH0414901A - Waveform generator - Google Patents

Abstract

PURPOSE:To make an output waveform continuous by inputting desired waveform data or reference data equivalent to 0V from a data selector corresponding to each D/A converter, converting the data into analog signals, adding the analog signals with an adder and outputting the sum to an output terminal. CONSTITUTION:A clock output from a clock generating section 23 is fed to a multiplexer 3, a D/A converter 4 and a selector control section 19 of each system directly, frequency-divided by a frequency divider section 24 into 1/N and the result is fed to a waveform memory 1 and an address generating section 2. The multiplexer 3 applies high speed processing to a waveform data read from the waveform memory 1 by multiplying the data by N according to the clock fed from a clock generating section 23. Thus, a waveform generator is realized, in which plural kinds of waveform sets are outputted at an optional point of time as a high speed consecutive waveform.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a waveform generator, and more particularly, to an improvement in switching output waveforms.

<Prior Art> When performing measurements using a waveform generator, there are cases where it is desired to continuously switch between a plurality of types of waveforms and apply them to the object to be measured.

As a device suitable for such a purpose, devices having configurations as shown in FIGS. 4 to 6 have been proposed.

■First conventional example In FIG. 4, waveform data corresponding to different output waveforms A, B, C1, etc. are stored in a plurality of waveform memories 1, and waveform data is read out into each of these waveform memories 1. Therefore, a common address is added from the address generator 2. The waveform data read from each waveform memory 1 is applied to the corresponding multiplexer 3 and converted into N-times high-speed waveform data. The output data of each multiplexer 3 is applied to a corresponding D/A converter 4 and converted into analog output waveforms A, B, C, . . . . Output waveforms A and B of each D/A converter 4.

C1... are added to the corresponding fixed contacts of the changeover switch 5. The movable contact of this changeover switch 5 is switched by a control section 6 in synchronization with an external signal.

As a result, a plurality of types of waveforms are selectively outputted to the output terminal 7 according to the switching of the changeover switch 5.

■Second Conventional Example In FIG. 5, a plurality of types of waveform data A, B, C, etc. are stored in the waveform memory 8, and the address for reading out the waveform data is stored in the address generation section It has been added since 9. The address generating section 9 switches and outputs addresses in synchronization with an external signal applied to the control section 10 so as to access an area in which desired waveform data is stored. The waveform data read from the waveform memory 8 is applied to the multiplexer 11 and converted into N-times high-speed waveform data. The output data of the multi-digitizer 11 is applied to the D/A converter 12, converted into an analog output waveform, and outputted to the output terminal 13.

(3) Third Conventional Example In FIG. 6, the same parts as in FIG. 4 are given the same reference numerals. In FIG. 6, the output data of each multiplexer 3 is applied to a data selector 14. The data selector 14 selects desired output data of the multiplexer 3 in synchronization with an external signal applied to the control section 15 and outputs it to the D/A converter 16. As a result, output terminal 1
A plurality of types of waveforms are outputted according to the selection of data selector 7.

<Problems to be Solved by the Invention> However, according to the first conventional example, since there is a time delay due to the switching operation of the changeover switch 5 (for example, even if a relay is used, ms auto occurs), the output terminal There is a problem that spikes occur in the signal waveform outputted to 7, and the output signal becomes discontinuous.

On the other hand, according to the second conventional example, since data is processed at high speed using a multiplexer, switching of memory addresses can only be performed at the end of each waveform data, and cannot be performed at high speed at any arbitrary point.

Furthermore, according to the third conventional example, although switching is possible at high speed at any time, there is a filter at the downstream stage of the D/A converter.
Since amplifiers, attenuators, etc. are connected, D/
The output signal output from the A converter 16 is limited to signals that can be commonly used by circuit elements connected to the subsequent stage, and the degree of freedom in the type of output signal is reduced.

The present invention has focused on these points, and its purpose is to provide a waveform generator that can output a plurality of types of waveforms as continuous waveforms at high speed while switching at any time.

Means for Solving the Problems The waveform generator of the present invention includes a plurality of waveform memories storing arbitrary waveform data, and a common address for reading the waveform data from these waveform memories. a plurality of data selectors each having one input terminal inputted with waveform data read from a corresponding waveform memory and the other input terminal inputted in common with reference data corresponding to 0■; A selector control part that serves as a secondary leg so that the waveform data of the waveform memory is selectively output from these data selectors, and a plurality of D/A converters that individually convert the data output from each data selector into analog signals. The present invention is characterized in that it is comprised of a converter, an adder that adds the output signals of each of these D/A converters, and a clock generator that provides a common clock to each part.

Function> Desired waveform data or reference data corresponding to OV is inputted to each D/A converter from its corresponding data selector and converted into an analog signal, and these analog signals are added by an adder and output. Output to the terminal.

As a result, the output signal of the system in which the reference data is selected becomes 0■, so it does not have a substantial effect on the output waveform, and the output waveforms of the system in which the waveform data is selected are added together and output. It turns out. Since each circuit is driven by a common clock, the output waveform is continuous.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram explaining the principle of the present invention, and the same parts as in FIG. 4 are given the same reference numerals. In the figure, waveform memory 1
Arbitrary waveform data is stored in each of these waveform memories 1, and an address for reading out the waveform data is commonly given to these waveform memories 1 from an address generator 2. Waveform data read from each waveform memory 1 is input to one input terminal of the corresponding data selector 18. Reference data corresponding to the OV of the output signal is commonly input to the other input terminal of each data selector 18. These data selectors 18 are controlled by a selector control unit 19 so as to selectively output waveform data from the waveform memory 1 in accordance with an external signal. The data output from each data selector 18 is individually applied to the D/A converter 4 and converted into an analog signal. The output signals of each of these D/A converters 4 are sent to an adder 20.
is added to and added to. The output signal of this adder 20 is outputted to an output terminal 22 via an amplifier 21. Each of these parts is supplied with a common clock from the clock generator 23, and operates in synchronization with a constant timing.

FIG. 2 is a configuration explanatory diagram showing one embodiment of the present invention.
This figure shows an example of a device for switching the waveform of system 1.2, and the same parts as in FIGS. 1 and 4 are given the same reference numerals. In FIG. 2, the clock output of the clock generator 23 is directly transmitted to the multiplexer 3. D/A converter4. The signal is applied to the selector control section 19, and is also divided into 1/N by a frequency dividing section 24 and applied to each waveform memory 1 and address generation section 2. The multiplexer 3 speeds up the waveform data read from the waveform memory 1 by N times according to the clock applied from the clock generator 23.

FIG. 3 is a timing chart explaining the operation of FIG. 2. The output of the clock generator 23 shown in (a) is applied to the frequency divider 24 and divided into N=8 as shown in (b). The address output from the address generator 2 is shown in (c).
It is updated in synchronization with the rising timing of the output of the frequency divider 24 as shown in FIG. According to the address output from the address generator 2, the output data of the waveform memory of one system 1 is rAJ, rB as shown in (d).

The output data of the waveform memory of the other system 2 is 1-CJ, r D J as shown in (e).
will be updated in this order. The waveform data of r A J and r BJ outputted from the waveform memory of the first system is added to the multiplexer of the first system, and the waveform data of r A J and r BJ are output as shown in (f).
1~A8J, 'Bl~B8. 8 times faster as
The waveform data of rC,, rp, output from the waveform memory of the second system is added to the multiplexer of the second system (
g) as shown in rc1~C8J, 'DI~D8. 8 times faster. On the other hand, the selector control unit 19 (
Control signals for complementary driving the data selectors 18 of each system as shown in (i) and (j) are output in accordance with an external signal shown in (h) that is applied asynchronously with the clock shown in (a). Here, each data selector 18 is (a)
The data should be switched in synchronization with the clock shown in . In the case of FIG. 3, each pig selector 18 is set to L active, so during the period when the control signal that drives the data selector of the first system is at L level, the control signal for driving the data selector of the first system is transmitted from the data selector to the D/A converter. The output data of the multiplexer is output and the data selector is used as the D/A in the second system.
The Ov reference data is output to the converter, and the period in which the control signal that drives the data selector of the second system is at L level is the second
In the first system, the data selector outputs the output data of the multi-blephr to the D/A converter, and in the first system, the data selector outputs reference data of 0 to the D/A converter. The output signals of the D/A converters 4 of each system are added to the adder 20 and added, but since the analog conversion output of the reference data of 0■ becomes 0■, the result is (k). As shown, the analog conversion output of the output data of the multi-breather of the other system becomes the addition output. That is, in the case of FIG. 3, "A1°A2J, rC3~C8, Di J
, '82 to B6J.

With this configuration, waveform data is switched electrically without using mechanical contacts.
High-speed switching is possible without the large time delay of conventional mechanical contacts.

Furthermore, since the waveform data is switched after the output data of the waveform memory is sped up, it is possible to switch the waveform data at any time in synchronization with the clock.

In addition, since the output of each system is converted to an analog signal by a D/A converter and then added, it is possible to connect a filter amplifier, attenuator, etc. according to the characteristics of the waveform output individually for each system. This increases the degree of freedom in device configuration.

Furthermore, since the waveform data is switched using a common clock, the output waveform is always continuous.

Although FIG. 2 describes an example in which output waveforms of two systems are selectively switched, it is also possible to selectively switch three or more systems. In that case, it is also possible to add output waveforms from multiple systems at the same time.

<Effects of the Invention> As described above, according to the present invention, it is possible to realize a waveform generation device that can output a plurality of types of waveforms or continuous waveforms at high speed without switching at any time.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration explanatory diagram showing an embodiment of the invention, Fig. 3 is a timing chart explaining the operation of Fig. 2, and Figs. 4 to 6 are FIG. 3 is a configuration explanatory diagram of each conventional device. 1...Waveform memory, 2...Address generation section, 4...
・D/A converter, 18...data selector, 19...
- Selector control unit, 20... Adder, 23... Clock generation \t-z''.

Claims (1)

[Scope of Claims] A plurality of waveform memories storing arbitrary waveform data, an address generation section that commonly provides an address for reading waveform data from these waveform memories to each waveform memory, and one input terminal is A plurality of data selectors are input with waveform data read from the corresponding waveform memory, and reference data corresponding to 0V is input in common to the other input terminal, and the waveform data of the waveform memory is selectively input from these data selectors. a selector control unit that controls the data output from each data selector, a plurality of D/A converters that individually convert the data output from each data selector into an analog signal, and an output signal of each of these D/A converters. A waveform generator comprising: an adder that performs addition; and a clock generator that provides a common clock to each section.