JPH041506B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory comprising bipolar transistors whose elements are isolated by an oxide layer.

Conventionally, semiconductor memories have been used for controlling computers, storing data, etc., and have played a major role in improving the performance of devices. Access time of 5ns or less 1~
The 16kb high-speed memory uses multi-emitter memory cells (SBD) with Schottky diode clamps.
cells) are used. On the other hand, PNP load memory cells are used for large capacity memories of 16 to 64 kb. In addition, as devices and systems become larger, the storage capacity of semiconductor memory per system increases, and the use of large amounts of small storage capacity semiconductor memory changes to the use of small amounts of large storage capacity semiconductor memory, resulting in improvements in cost and performance. Improving.

In such a large-capacity semiconductor memory, the chip area generally increases in proportion to the storage capacity, so there are problems in that the yield of non-defective products and the processing speed, so-called access time, decrease.

Figure 1 shows the number of transistors for each function in a silicon semiconductor memory.The number of transistors used in the peripheral circuit section is almost constant regardless of the storage capacity, as shown by curve 11, but the number of transistors used in the memory cell section is shown by curve 11.
2, it shows that it increases in proportion to the storage capacity. Furthermore, FIG. 2 shows a breakdown of the access time by function of the silicon semiconductor memory, and it can be seen that most of the access time is determined by the peripheral circuit propagation time. Therefore, in order to manufacture a high-capacity silicon semiconductor memory that can operate at high speed and has a high yield, it is necessary to improve the yield of the memory cell section that uses many transistors, as shown in FIGS. 1 and 2. It is necessary to improve the speed of the peripheral circuitry that takes up most of the access time.

By the way, as is well known, transistors in which elements are isolated by an insulating layer constituting a silicon semiconductor memory use a silicon nitride film as a mask to form a silicon oxide film as an insulating layer by a selective oxidation method. However, the oxide film is also formed under the mask area. (Due to its shape, this oxidized film is called a bird's beak.) The presence of this bird's beak impairs the characteristics of the memory, but attempts to reduce it will reduce the yield of good products.

FIG. 3 is a sectional view of a main part of a conventional silicon transistor with a large bird's beak. An N-type buried layer 32 and a bird's-eye layer are formed on a P-type silicon substrate 31.
N surrounded by silicon oxide film 33 with a large peak
Type epitaxial island (collector region) 3
4 (this epitaxial layer constitutes the semiconductor body forming the transistor), a P type base region 35 and an N type emitter region 36. Here, the size of the bird's beak is defined as the distance between the ends of the silicon oxide film 33 on the emitter region 36 and the point where the silicon oxide film 33 contacts the lower surface of the collector region 34, respectively, perpendicular to one main surface of the semiconductor substrate. is defined as the distance L ₁ ′. The yield is better if the emitter region 36 is formed at a sufficient distance from this bird's beak, but the base-collector junction capacitance (hereinafter abbreviated as C _BC ) and the collector-substrate capacitor (hereinafter abbreviated as C _CS ') becomes larger, which causes an increase in access time.

FIG. 4 is a sectional view of a main part of a conventional small silicon transistor with a bird's beak L' ₂ . It consists of an N-type epitaxial island (collector region) 44 surrounded by an N-type buried layer 42 and a silicon oxide film 43 with a small bird's beak on a P-type silicon substrate 41, a P-type base region 45, and an N-type emitter region 46. ing. It is better to form the emitter region 46 away from the bird's beak, but since the bird's beak is small, C _BC and
C _CS ', etc. can be made smaller than the transistor shown in FIG. 3, but it is difficult to form an emitter and a high yield is difficult due to leakage between the collector and the emitter or between the base and the emitter. In addition, the third
In the figure and FIG. 4, 37 and 47 are emitter electrodes. (The base and collector electrodes are taken out from separate locations and are not shown.

FIG. 5 shows an example of the configuration of a conventional silicon semiconductor memory using the transistors shown in FIGS. 3 and 4 independently. It is composed of a memory cell section 52 and a peripheral circuit section 53 including input/output circuits and the like on a silicon semiconductor substrate 51. Furthermore, since all the transistors have the same design and are formed in the same process, they are characterized by having bird's beaks of the same length. Therefore, conventional semiconductor memories using transistors with a large bird's beak as shown in Figure 3 will have a slow speed, and those using transistors with a small bird's beak as shown in Figure 4 cannot be expected to have a high yield of good products. It has its drawbacks.

The purpose of the present invention is to use a structure with a good yield for memory cell transistors, which are used in large quantities, in order to improve yield, and to use transistors in peripheral circuits that affect speed to have a structure that allows high-speed operation. The object of the present invention is to provide a large-capacity semiconductor memory that satisfies both speed and yield.

The memory of the present invention is a semiconductor memory comprising transistors formed on one main surface of a semiconductor substrate and separated by an oxide layer, wherein the transistor is located at an end portion of the oxide layer above an emitter region of the transistor. and two types of transistors, in which the distance L between the planes passing through the point where the oxide layer contacts the lower surface of the collector region of the transistor and perpendicular to one main surface of the semiconductor substrate differs from each other by approximately 30% or more. It's natural.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 6 is a chip configuration diagram of one embodiment of the present invention. A memory cell portion 62 is formed on an N-type silicon substrate 61.
and a peripheral circuit section 63 including input/output circuits and the like. The memory cell section 62 uses an L1 transistor with a large bird's beak, as shown in FIG. 7, and the peripheral circuit section 63 uses an _L1 transistor, as shown in FIG. 8. As such, _L2 transistors with small bird's beak are used. In Figures 7 and 8, 71, 8
1 is an N-type silicon substrate, 72 and 82 are N-type buried layers, 73 and 83 are silicon oxide films for insulation isolation, and 7
4, 84 are N-type epitaxial islands (collector regions), 75, 85 are P-type base regions, 7
6 and 86 are N-type emitter regions, and 77 and 87 are emitter electrodes.

In other words, in this embodiment, as shown in FIG. 1, the number of cells used increases in proportion to the storage capacity, so a high yield is expected for the memory cell section 62, which affects the yield of non-defective memory chips. A transistor with a large bird's beak is used, and at the same time, a transistor with a small bird's beak is used for the peripheral circuit section 63 that regulates the memory speed, as shown in FIG. Therefore, the speed characteristics do not deteriorate when trying to achieve a high yield as in the past, and a large capacity semiconductor memory with high speed characteristics and high yield can be obtained.

By the way, in order to ensure this effect of this embodiment, the difference in the size of the bird's beak must be greater than a certain level. Figure 9 shows the bird's beak size ratio (L ₂ /L ₁ ) (see Figures 7 and 8) of two types of transistors with different bird's beak sizes, the memory yield, and the access time T. This shows an example of the relationship with _AA . That is, as L ₂ /L ₁ becomes smaller, the yield decreases and the access time also decreases.
For example, when L ₂ /L ₁ = 70 (%), the yield drops from about 85% to about 55%, and the access time decreases from 1 to 0.6
It's getting smaller. Therefore, in the above embodiment, L ₂ /L ₁ = 70% (that is, 30% different from each other), so the access time is 0.6 faster than the conventional 1, and the yield is about 85%. High yield memory can be obtained. In this way L ₂ /
If the value of L ₁ is approximately 70% or less, that is, if the sizes of the bird's beaks differ from each other by approximately 30% or more, a memory with high speed characteristics and high yield can be reliably obtained.

A manufacturing method for forming transistors with different bird's beaks on the same substrate will be explained in order of steps with reference to FIGS. 7 and 8.

First, N ⁺ type buried layers 72 and 82 are selectively formed on P type silicon substrates 71 and 81, and N type epitaxial layers 74 and 84 are grown.

Next, a silicon oxide film and a silicon nitride film are deposited on the entire surface, the silicon nitride film in the memory cell area is selectively etched, and then a first thermal oxidation is performed to oxidize to half the thickness of the N-type epitaxial layer 74. .

Next, the silicon nitride film, silicon oxide film and N-type epitaxial layer 84 in the peripheral circuit area are etched to half the thickness.

Next, a second thermal oxidation is performed to form silicon oxide films 33 and 43 having different bird's beaks.

Thereafter, the base, emitter, etc. are formed using a well-known manufacturing method to complete the element section.

As explained in detail above, according to the present invention, a transistor with a large bird's beak that is easy to manufacture can be used in the memory cell section that regulates the chip yield, and high-speed characteristics can be obtained in the peripheral circuit section that regulates the processing speed of the memory. Since a transistor with a small bird's beak and two types of transistors are used in the right places, a high-speed, high-yield, large-capacity semiconductor memory can be obtained.

[Brief explanation of drawings]

Figure 1 shows the number of transistors by function of silicon semiconductor memory, Figure 2 shows the breakdown of access time, and Figures 3, 4, and 5 show the configuration pattern of a conventional silicon semiconductor memory. and sectional views of main parts of the transistors used, Figures 6, 7, 8.
The figure shows the configuration pattern of a silicon semiconductor memory according to an embodiment of the present invention and a cross-sectional view of the main parts of the transistor used, and _{FIG .} It is a relationship diagram of access time. 31, 41, 71, 81... P-type silicon substrate, 32, 42, 72, 82... N-type buried layer,
33, 43, 73, 83...silicon oxide film, 3
4, 44, 74, 84...N-type epitaxial island (collector region), 35, 45, 75,
85...P type base region, 36, 46, 76, 8
6... N-type emitter region, 51, 61,... N-type silicon semiconductor substrate, 52, 62... Memory cell section, 53, 63... Peripheral circuit section, L ₁ ′, L ₂ ′, L ₁ ,
L ₂ ...The size of a bird's beak.

Claims (1)

[Claims] 1. In a semiconductor memory consisting of a transistor formed on one main surface of a semiconductor substrate and separated by an oxide layer, the transistor includes an end portion of the oxide layer above the emitter region of the transistor and the oxide layer. are in contact with the lower surface of the collector region of the transistor, and the distances L ₁ and L ₂ between the planes perpendicular to one main surface of the semiconductor substrate differ from each other by approximately 30% or more, and the distance L ₁ is large. The memory cell part consists of two types of transistors: a transistor and a small L ₂ transistor.
Consists of L ₁ transistor, peripheral circuit section is L ₂
A semiconductor memory characterized by comprising transistors.