JPS60211969A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor technology and to technology that is effective when applied to the formation of capacitors on semiconductor substrates, such as speed-up capacitors in memory cells in bipolar memory and memory The present invention relates to techniques that are effective for forming charge storage elements of cells.

[Background Art] As a structure of a memory cell in a bipolar semiconductor memory, for example, the structure shown in FIG. 1 is known ("Memory", p. 94, published by the Institute of Electronics and Communication Engineers).

This memory cell includes multi-emitter 1 to transistor Q1 . In parallel with the load resistor R1°R2 connected between the collector of Q2 and the word line W,
By connecting Schottky barrier diodes D and +'D2 with low forward resistance and forward voltage, the read current is increased and the signal rises faster, resulting in lower power consumption and write/read speeds. The aim is to speed up the process.

By the way, it has been found that in a memory cell having the circuit type described above, the read speed can be increased by increasing the area of the Schottky barrier diodes D1 and D2.

That is, Schottky barrier diode D x ,
As D2 increases, its parasitic capacitance increases, so
As shown by broken lines in FIG. 1, the barrier diodes D1. The configuration is the same as connecting capacitors C1+C2 in parallel with D2. Then, when the word line W is brought to a high level during reading, the capacitor performs a high-speed switching operation (resistance becomes zero), and nodes no and nl (especially low-side nodes) rise quickly and overload. Shoot waveform is improved. In other words,
Schottky barrier diode D1. The parasitic capacitance of D2 acts as a speed-up capacitor, increasing the read speed. Furthermore, the operating margin of the two circuits is improved.

Therefore, the present inventor developed a Schottky barrier diode D1. Increase the occupied area of D2 to 0°35 to 0.4
A memory cell structure that can be read at high speed has been developed by forming the memory cell to have a capacitance on the order of pF.

However, in the above memory cell structure, the Schottky barrier diode D1 occupies a large area.
It has been found that r D 2 occupies nearly 40% of the occupied area of the memory cell, which is disadvantageous in that it impedes higher integration as memory capacity increases.

On the other hand, the applicant first cut away the portion that will become the element isolation region to form a U-shaped groove (hereinafter referred to as a U-groove), and
He proposed an isolation technology called the U-groove isolation method, in which an oxide film is formed inside the trench and then the inside of the U-groove is filled with polysilicon (polycrystalline silicon) to create an element isolation region. -168355).

[Object of the Invention] An object of the present invention is to provide a semiconductor technology that is more effective than the conventional technology.

Another object of the present invention is to increase the read speed without increasing the area occupied by the memory cell when applied to a flip-flop type memory cell in a bipolar memory, for example.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, the present invention uses the above-mentioned U as a method for separating elements.
Increasing the area of the Schottky barrier diode by applying the groove isolation method and using the capacitance between the dielectric filled in the U-groove and the semiconductor substrate as a speed-up capacitor in bipolar memory. Accordingly, the above object of providing a memory cell structure that occupies a small area and can be read at high speed is achieved.

This invention will be specifically described below with reference to the drawings.

[Embodiment] FIG. 2 is a plan view showing an embodiment in which the present invention is applied to a memory cell of a bipolar type memory, and FIG. 3 is a sectional view taken along the line ■-■.

In this example, a Schottky barrier diode I)
1. Adjacent to D2, a plurality of U-grooves u1+u2+... are arranged in a stripe pattern, although not particularly limited, in an area approximately the same size as the area occupied by this Schottky barrier diode. The capacitor area Ac1. A
c2 is provided.

Also, the same Schottky barrier diode D1. D
Adjacent to 2, a multi-emitter transistor Q 1 constitutes a flip-flop. Q2 is formed, and the memory cells MC are laid out in a rectangular shape as shown in FIG. 2, and the memory cells MC are arranged continuously in the vertical and horizontal directions to form a memory cell array. The implementation efficiency is improved.

Note that, although not particularly limited, the capacitor area A c
1 (A C2), the Schottky barrier diode D1 (D2), and the transistor Q1 (Q2), as well as to facilitate wiring connections with word lines and data lines. The inside of the memory cell MC is divided as shown by the chain line S in FIG. 2, and includes a Schottky barrier diode D1 (D2) connected to the transistor Q1 (Q2) and a capacitor area A c
1' (A C2) are laid out in an L-shape. The periphery of the memory cell MC is separated by a relatively deep U-groove isolation region, and the capacitor region AC1 (AC2), the Schottky barrier diode DI (D2), and the transistor Ql (Q2) are separated from each other by a relatively deep U-groove isolation region. They are separated by a relatively shallow U-groove isolation region. The capacitance value of the capacitor can be set to a desired value by appropriately adjusting the depth of the U-groove or adjusting the thickness of the oxide film or Si3N4 film within the U-groove.

Note that in FIG. 2, symbols E and C indicate the emitter region and collector region of the transistor, respectively.

Next, a specific structural example of the memory cell MC will be explained using the cross-sectional view of FIG. 3.

For example, an N+ buried layer 2 formed by thermally diffusing N-type impurities using an oxide film or the like as a mask is provided on a semiconductor substrate 1 made of P-type silicon. Also, N
An N- type epitaxial layer 3 formed by vapor phase growth is provided on the + buried layer 2.

At the peripheral edge of the memory cell, there are relatively deep U-groove isolation regions 4a, 4a that penetrate the N- type epitaxial layer 3 and the N+-type buried layer 2 and reach the substrate 1.
are formed, and relatively shallow U-groove isolation regions 4b, 4 are formed at the boundaries of each element region in the memory cell and at the capacitor region Ac.
b and U groove separators 4c, 4c, . . . are formed.

The U-groove isolation regions 4a, 4b and the U-groove isolation body 4c are as follows:
For example, using a nitride film or the like formed on the main surface of the semiconductor substrate 1 (the surface of the epitaxial layer 3) as a mask, U etching is performed on the main surface of the substrate by hydrazine etching and dry etching.
After forming the grooves, an insulating film 5 such as an oxide film is formed inside the U-grooves, and then polysilicon (polycrystalline silicon) is deposited by CVD to form a polysilicon film inside each of the U-grooves. It is formed by filling.

In the above case, the dry etching is divided into two times, and during the first dry etching, the boundaries between elements in the memory cell are covered with photoresist, etc., and during the second dry etching, both U-groove portions are simultaneously etched. By etching, two U-grooves with different depths can be formed.

As mentioned above, after each U-groove is filled with polysilicon, the polysilicon on the surface is removed by etching and flattened, and then thermal oxidation is performed to form an oxide film 7 on the surface of the polysilicon. and cover with a lid.

Then, N-type impurity ions are implanted into the portion that will become the collector outlet and are diffused by heat treatment to form the N-type collector outlet 8.

Next, P-type impurity ions are implanted into the portion that will become the base region, and their thermal diffusion is performed, and N is implanted into the portion that will become the emitter region.
Perform ion implantation and thermal diffusion of type impurities.

As a result, as shown in FIG. 3, a base region 9 and emitter regions 10 and 10 are formed, and a bipolar transistor is constructed.

In the above case, an isolation region is not formed at the boundary between the base region 9 and the collector outlet 8, but an oxide film isolation region consisting of the same isolation region as the above-mentioned shallow U-groove isolation region 4b or LOGO 8 is formed at this boundary. may be provided.

Next, the insulating film 11 such as an oxide film on the main surface of the substrate is partially removed to form contact holes in each electrode part of the transistor. At this time, the Schottky barrier diode D is The portion of the insulating film 11 to be formed is removed. Then, aluminum or the like is deposited on the surface and photo-etched to form the epitaxial region 3a surrounded by the shallow U-grooves 4b, 4b, as shown in FIG. An aluminum electrode 13d is formed in contact with the surface, thereby forming a Schottky barrier diode D.

Further, when forming the contact hole, the U-groove isolation bodies 4c, 4c, . . .
For the U-groove separators 4c, 4c, . ...make contact with the polysilicon inside. This is because the contact area between the U-groove separator 4c and the substrate is large.

A relatively large capacitance is generated between the polysilicon layer as an internal dielectric and the substrate 1, and this is connected to the electrode 13d of the Schottky barrier diode D.

The other end of the capacitor of the U-groove separator 4c is connected to the collector of the transistor via the N+ buried layer 2. Also, although not shown in Figure 3,
Resistors R1 and R2 made of diffusion layers are formed on the main surface of the substrate in the transistor region Q.

As a result, as shown in FIG. 4, the Schottky barrier diode D1. A memory cell structure is realized in which speed-up capacitors C1 and C2 are connected in parallel with D2. Moreover, in this case, the capacitance of the U-groove separator 4c, which has a large contact area with the substrate, is increased by the speed-up capacitor C1,
Since it is used as C2, the area efficiency is better than when using the capacitance of a Schottky barrier diode.

For example, if you want to achieve a capacitance of about 0.3 to 0.4 PF for the speed-up capacitors C1 and C2, if you use the capacitance of a Schottky barrier diode, the Schottky barrier diode will occupy about 40% of the cell area. In contrast, if the U-groove separator 4C as in the above embodiment is used, it is only necessary to provide a capacitor region approximately 10% of the cell area.

In the above embodiment, the U-groove separators 4C are formed in a stripe shape within the capacitor region Ac, but the U-groove separators 4C may be formed in a lattice shape, a mesh shape, a honeycomb shape, or the like. Further, the depth of the U-groove can be made deep or shallow.

Further, in the above embodiment, the semiconductor constituting the diode that is in contact with the electrode 13d of the Schottky barrier diode and the semiconductor between the U-groove separator 40 are used as the epitaxial layer 3, but these parts are At the same time as the N-type impurity ion implantation into the opening 8, ions may be implanted to make it N+ type.

Furthermore, in the above embodiment, a capacitor region made of a U-groove isolation body is provided in the memory cell, but the U-groove isolation region 4
In a semiconductor integrated circuit in which elements are isolated by a, it is also possible to actively utilize the capacitance in such a U-groove for element isolation.

In semiconductor integrated circuits using aluminum double-layer wiring technology,
An interlayer insulating film is formed on the aluminum electrodes 13b to 13e shown in FIG. 3, and a second layer of aluminum wiring is formed thereon.

Also, instead of aluminum, platinum silicon (P
t-3i) or titanium tungsten (Tie), etc., to form the Schottky barrier diode electrode 13d.
Ao [Effect] In addition to applying the above-mentioned U-groove isolation method as an isolation method between elements, the capacitance between the dielectric material filled in the U-groove and the semiconductor substrate can be reduced in bipolar memory. Since it is used as a speed-up capacitor, the speed-up capacitor can be configured without increasing the area of the Schottky barrier diode, which enables high-speed reading and high integration of memory cells in bipolar memory. , it is possible to reduce the chip size.

The above capacitor can also be used as a capacitor for improving circuit margin and alpha ray resistance.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the U-groove isolation region and the U-groove separator have a structure in which the inside of the oxide film formed in the U-groove is filled with polysilicon as a dielectric. A structure may be used in which a film and a nitride film are formed in two or three layers, and a dielectric is filled inside the film, and the dielectric is not limited to polysilicon. Furthermore, the element isolation method may be an oxide film isolation method or the like instead of the U-groove isolation method.

[Field of Application] The above description has mainly focused on the application of the invention made by the present inventor to bipolar memory, which is the field of application that formed the background of the invention. It can be used for all semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of the structure of a memory cell in a conventional bipolar memory, and FIG. 2 is an explanatory plan view showing an example in which the present invention is applied to the structure of a memory cell in a bipolar memory. , FIG. 3 is a sectional view taken along the line ■-■ in FIG. 2, and FIG. 4 is a circuit diagram showing an example of the structure of a memory cell in a bipolar memory to which the present invention is applied. 1... Semiconductor substrate, 2... N0 buried layer, 3...
...N-type epitaxial layer, 4a, 4b...U groove isolation region, 4c...U groove separator, 5...insulating film (oxide film), 6...dielectric material ( polysilicon), 7.
...Oxide film, 8...Collector drawer opening, 9...
・Base region, 10...Emitter region, 11...
・Insulating film, 13b, 13c,, 13e...Transistor electrode, 13d...Schottky barrier diode electrode, Ql, Q2...Multi-emitter transistor, Dl, D2...Schottky barrier・Diode, cl, 'c2...Speed-up capacitor, W...Word line, Ac1゜A C2...Capacitor area. Figure 1 Figure 2

Claims (1)

[Claims] 1. An isolation region is formed by digging a trench between active regions of elements formed on the main surface of a semiconductor substrate, forming an insulating film on the inside, and then filling the trench with a dielectric material. A semiconductor device characterized in that a capacitance between the dielectric body in the isolation region and the semiconductor substrate is used as a capacitor constituting a circuit. 2. The capacitance between the dielectric material and the semiconductor substrate in the isolation region is used for speed-up capacitors constituting memory cells in bipolar memory, circuit margins, and for improving alpha ray resistance. A semiconductor device according to claim 1, characterized in that: 3. The above-mentioned capacitor utilizes the capacitance between the semiconductor substrate and a dielectric filled in a groove formed separately from the isolation region. 2. The semiconductor device according to item 2.