JPH0415262U - - Google Patents

Info

Publication number
JPH0415262U
JPH0415262U JP5504790U JP5504790U JPH0415262U JP H0415262 U JPH0415262 U JP H0415262U JP 5504790 U JP5504790 U JP 5504790U JP 5504790 U JP5504790 U JP 5504790U JP H0415262 U JPH0415262 U JP H0415262U
Authority
JP
Japan
Prior art keywords
insulating layer
thickness
ceramic substrate
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5504790U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5504790U priority Critical patent/JPH0415262U/ja
Publication of JPH0415262U publication Critical patent/JPH0415262U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】
第1図はこの考案の実施例の要部を示す縦断面
図、第2図はこの考案を得る途中の段階で考えら
れたHICの要部を示す縦断面図、第3図は第2
図の印刷抵抗体3の平面図、第4図は従来のHI
Cの要部を示す縦断面図である。

Claims (1)

  1. 【実用新案登録請求の範囲】 スルホールセラミツク基板の一方の面に回路部
    品が実装され、他方の面に印刷抵抗体が形成され
    た混成集積回路において、 絶縁体層が上記スルホールセラミツク基板の他
    方の面に上記印刷抵抗体及びその近傍を除いて形
    成され、 その絶縁体層の厚味は上記印刷抵抗体の厚味よ
    り大きく設定され、 その絶縁体層の表面がパツケージへ接着固定す
    る場合の接合面とされることを特徴とする、 混成集積回路。
JP5504790U 1990-05-25 1990-05-25 Pending JPH0415262U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5504790U JPH0415262U (ja) 1990-05-25 1990-05-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5504790U JPH0415262U (ja) 1990-05-25 1990-05-25

Publications (1)

Publication Number Publication Date
JPH0415262U true JPH0415262U (ja) 1992-02-06

Family

ID=31577652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5504790U Pending JPH0415262U (ja) 1990-05-25 1990-05-25

Country Status (1)

Country Link
JP (1) JPH0415262U (ja)

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