JPH04155457A - Memory access control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] [Object of the present invention] Regarding a two-cycle cache memory access control circuit, an object of the present invention is to quickly and accurately perform the next memory access process after a mishit read to the cache. In a two-cycle cache memory access control circuit that sends out an address in the first cycle and overwrites with the first cycle of the next access in the second cycle to transfer data, if a miss occurs in the first cycle, the second cycle 5TI that generates a signal to suppress the stage transition of
NH generation circuit and MRQOK generation that turns off the memory access request permission signal (MRQOK signal) in the event of a miss and turns on the MRQOK signal from off in the cycle immediately before the last data read from the main memory reaches the cache memory. The present invention is configured to include a 5TINH suppressing circuit and a 5TINH suppressing circuit that stops the stage transition suppressing signal of the 5TINH generating circuit when the MRQOK signal changes from off to on.

[Industrial Application Field] The present invention provides a two-cycle cache memory access method in which an address is sent in the first cycle and data is transferred in the second cycle, overlapping with the first cycle of the next access. The present invention relates to a memory access control circuit for quickly and accurately performing the next access in the event of a memory mishit.

[Conventional technology]

In many data processing systems, a cache device is added as a means to substantially reduce access time to main memory. Particularly in systems that require high speed, two-cycle access pipeline control is adopted in which the data transfer cycle and address transmission for the next access overlap to make efficient use of cache memory. .

In this two-cycle access pipeline control,
Since the address for the next access 7 is being sent while the sent address is being judged as a hit, control in the event of a miss becomes complicated, and considerable overhead is generated until the next access is resumed. I started to do it.

Next, a conventional two-cycle memory access control system will be described with reference to FIGS. 6 to 9. FIG. 6 is an explanatory diagram of stage transition, FIG. 7 is an explanatory diagram of a conventional memory access control system, FIG. 8 is an operation timing chart of a conventional memory access control circuit, and FIG. 9 is an explanatory diagram of a conventional memory access control system. FIG. 6 is an explanatory diagram of an operation timing chart when there is a mishit and invalidation.

In FIG. 7, 21 is a main memory interface controller (indicated by MM interface controller).
It performs interface control between the main memory and a memory access control circuit (not shown). Reference numeral 211 is a monitoring directory provided in the MM interface controller 21, and the monitoring directory 211 is a monitoring directory provided in the MM interface controller 21.
Monitor writes by MA (direct memory access).

MAB is an address bus between the MM interface controller 2I and the main memory, and MAD is a data bus between the MM interface controller 21 and the main memory.

Reference numeral 22 denotes a directory memory, also called a tag memory, in which addresses of data registered in the cache memory are stored.

HIT is a hit signal that indicates that the cache memory has been hit, and indicates 1 when there is a hit, and indicates 0 when there is a miss.

Reference numeral 23 is a hit number holding register (indicated by HIT register), in which hit information outputted from the directory memory 22 in the first cycle is stored. If the directory memory 22 is composed of a plurality of blocks, the hit information indicates the number of the hit block. This hit information selects the memory area corresponding to the block in the cache memory.

Reference numeral 24 denotes a Hanwha memory for cache (hereinafter referred to as cache memory), which is composed of high-speed memory elements such as bipolar transistors, and stores accessed data in the main memory.

25 is a cancel address holding register (indicated by cMA register), which stores the address for accessing the cache memory 24 sent out in the first cycle and holds it until the next second cycle.

A processor 26 executes stage processing in each cycle and also controls the operation of the entire system.

261 is an address register provided in the processor 26, in which addresses for accessing the main memory, directory memory 22, and cache memory 24 are stored.

262 is a data register provided in the processor 26, in which data read from the cache memory 24 or main memory is stored.

AB is an address bus between the MM interface controller 21 and the processor 26, CB is a control signal bus to which various control signals are transferred, and DB is a data bus to transfer data between the MM interface controller 21 and the processor 26. .

INVL is an invalidation signal that invalidates data registered in the cache memory 24. When this invalidation signal is received, an invalidation flag (not shown in the figure) is set in the area corresponding to the invalidation target data area in the directory memory 22. ) will be erected.

Reference numeral 30 denotes a memory access control circuit, which is provided within the MM interface controller 21 and receives instructions from the processor 26 to control memory access to the main memory. Various control signals generated by the memory access control circuit 30 and their memory access control operations will be explained later in the operation description. Note that various control signals shown in parentheses within the block of the memory access control circuit 30 indicate various control signals generated inside the memory access control circuit 30.

Next, the stage transition controlled by the memory access control circuit of FIG. 7 will be explained with reference to the stage transition explanatory diagram of FIG. 6.

In FIG. 6, in the first memory request stage, the processor 26 sends out a memory access request signal MRQ requesting access to a main memory (not shown).

When the access request to the main memory is accepted, in the next first stage, processing for sending an address for accessing the main memory and hit determination processing for the cache memory are performed. 5TGI is a first stage signal that activates the first stage and is generated by the memory access control circuit 30.

In the next second stage, processing is performed to transfer the hit data to the cache memory.

5TG2 is a second stage signal that activates the second stage and is generated by the memory access control circuit 30.

Next, the memory access control operation will be explained with reference to the operation timing chart of FIG. In Figure 8,
CLKI is a clock that regulates the timing of each operation performed within the memory access control circuit 30, and is generated in synchronization with a system clock common to the system. τ1,
τ2 etc. indicate each cycle of the clock CLKI (the 8th
Figure (a)).

When accessing a main memory (not shown), the processor 26 sends out a memory access request signal MRQ in the memory request stage (FIG. 8(b)). Now, cycles τ1, τ of clock CLK1
2 and τ, consecutive memory access requests MRQ
occurs, and these are designated as memory access request signals MRQ■, MRQ■, and MRQ■ as shown in FIG. 8(b).
)).

In response to the first memory access request signal MRQ issued in the τ1 cycle, when the memory access request permission condition is satisfied, the memory access control circuit 30 issues a memory access request permission that allows the memory access request in the same τ1 cycle. The signal MRQOK (indicated by the MRQOK signal) is turned on (FIG. 8(c)).

When this MRQOK signal is turned on, the memory access control circuit 30 outputs a first stage signal 5TGI (S
TGI (indicated by ■) is generated and sent to the processor 26 via the control signal bus AB (■ in FIG. 8(d)).

Upon receiving this first stage signal 5TGI■, the processor 26 performs the first stage processing in the second cycle τ2, and sends out the address for accessing the main memory in the address register 261 via the address bus AB. In addition, the cache memory 24
Performs a human judgment for.

That is, the address sent by the processor 26 first accesses the directory memory 22.

When the address corresponding to the address to be accessed is in the directory memory 22, the hit signal HIT becomes 1,
Indicates that the cache memory has been hit. If the address corresponding to the accessed address does not exist in the directory memory 22, the hit signal I (IT) becomes O, indicating that there has been a miss in the cache memory.

This hit signal HIT is sent to the memory access control circuit 30 via the MM interface controller 21. Further, hit information of the cache memory is stored in the HIT register 23. If directory memory 22 consists of multiple blocks, this hit information indicates the number of the hit block. The hit information in the HIT register 23 is sent to the cache memory 24, and when the hit signal HIT is 1 (hit to the cache memory), the area of the cache memory 24 corresponding to the hit block number of the directory memory 22 is selected. .

In the following, cases in which the cache memory 24 is hit and cases in which it is a miss will be explained separately.

(1) When the cache memory is hit When the cache memory 24 is hit, that is, the hit signal HIT
is 1, the memory access control circuit 30 outputs the second stage signal 5TG2 in the next cycle τ in synchronization with the clock CLKI that defines the operation timing of the circuit.
(denoted as STG2) and sends it to the processor 26 via the control signal HAS CB (■ in FIG. 8(e)).

Upon receiving this second stage signal 5TG2■, the processor 26 performs second stage processing in the second cycle τ3, as shown in FIG.
The data hit is read and transferred to the data register 262 of the processor 26 via the data bus DB.

On the other hand, in this cycle τ3, the processing of the second cycle (second stage) for the first memory access request signal MRQ overlaps with the processing of the first cycle (first stage) for the next memory access request signal MRQ■. Processing is performed (5T in Figures 6 and 8(d))
(See G1■ and (e) 5TG2■).

The first cycle of the next memory access request signal MRQ■ (
τ in Figure 8(d), the first stage of the cycle 5TG1■
), when the cache memory 22 is hit, the memory access request signal MR is activated in the following 4 cycles.
The second cycle of Q■, that is, the second stage 5TG2
Processing (2) is executed.

Similarly, when the cache memory is hit, the processes of the first stage 5TGI and the second stage 5TG2 are sequentially executed for each memory access request signal MRQ (not shown).

(2) In the case of a cache memory miss In the processing of the first stage 5TGI■ of the memory access request signal MRQ■ performed at τ2, the processor 26
Suppose that the address sent from the cache memory 24 misses, the hit signal HIT is
2 becomes O (Fig. 8 (j)).

The memory access control circuit 30 has a hit signal HIT of 0.
(Mishit), the clock inhibit signal CLKSP is generated in the τ3 cycle.

Furthermore, the memory access control circuit 30 receives a hit signal HI.
When T is 0 (miss) and the first stage 5TG1■ of the continuous memory access request signal MRQ■ is on (τ3 cycle in FIG. 8(d)), the stage transition inhibition signal 5TINH is activated from the τ4 cycle. Turn on (Figure 8 (])).

As a result, the value of the first stage signal STG1■ of the memory access request signal MRQ■ output from the memory access control circuit 30 is continuously 1 from the cycle onwards.
(FIG. 8(d)), the second stage signal 5TG2■ of the memory access request signal MRQ■ is
After the τ3 cycle, the value 1 is continuously held (FIG. 8(e)).

Furthermore, by generating the clock inhibit signal CLKSP in the 3rd cycle as described above, the generation of clocks after τ4 is inhibited, and the control operation of the memory access control circuit 30 after the τ4 cycle is interrupted at - time. (
Figures 8(n) and (a)).

While the control operation of the memory access control circuit 30 is temporarily suspended due to a miss in the cache memory 24, the MM interface controller 21 reads the missed data from the main memory (not shown) and connects the data bus DB. The read data is transferred to the processor 26 via the read data, and the read data is registered in the cache memory 24, and the tag information such as its address is registered in the directory memory 22. This data transfer process is performed between τ4 and τ6 cycles.

Data reading from the main memory is performed in block units, and multiple words (D■-1 in the figure) containing mishit data in response to memory access request signals M R, Q■.
~D■-4 words) are read and the processor 2
6 and the cache memory 24 (Fig. 8 (g)
)).

When data in each block is read from the main memory, block read signals BLKRDI to BLKRD4 are sent to the memory access control circuit 30 in response to data words D■-1 to D■-4 from the MM interface controller 21. Figure 8 et al.) and (i)
block read signals BLKRD3 and BLKRD
4 is shown.

When the first data D■-1 is transferred, the processor 2
6 can move on to the next process, so the memory access control circuit 3
The suppression of the 0 clock CLK may be stopped and its control resumed. Therefore, MM Zein Face Controller 21
Then, the start signal 5TART is turned on (τ7 in FIG. 8 Φ)).

The memory access control circuit 30 receives a start signal 5TAR.
When T becomes 1, the clock inhibit signal CLKSP is set to 0 in the next τ8 cycle and the clock CLK is restarted (
8(a) and (n), τ, cycle).

At the point when the transfer of the mishit data is completed, that is, when the data D■-4 is transferred (τ, the end of the cycle), there is no longer a need to suppress the stage transition, and the next τ
, stage transition may start from the second cycle.

However, in the memory access control circuit 30, when the block read signal BLKRD3 indicating the transfer period of the third word of block read data D■-3 is turned on at τ1°,
In the next τ12 cycle, which is one cycle later than the next τ11, the stage transition inhibition signal 5TINH is turned O (off) (FIG. 8 (1)). The reason for delaying by one cycle will be explained later).

As a result, the first stage ST+l, which is the stage processing related to the memory access request signal MRQ, continues to be on until τ, 2 cycles, and the cache memory 2
A valid hit determination is made at τ12 when the hit determination for 4 becomes valid, and the second stage 5TG2■ is executed as positive I in the τ1 cycle (FIG. 8(d), (
e), (j), (goods)).

In the τ1 cycle, as in the case of the above-mentioned τ3 cycle, the second cycle processing (second stage 5TG2) corresponding to the memory access request signal MRQ■ and the bright 1 cycle of the next memory access request signal MRQ-■ are performed. (1st stage 5TG1■) is performed in parallel (Fig. 8(d)
), (e), (j), Qc)).

Next, the next τ12, which is one cycle later than τ, 1 cycle
cycle, the stage transition inhibit signal ST I NH is set to O(
The reason for turning off) will be explained with reference to FIG.

FIG. 9 shows an operation timing chart similar to FIG.
The operation content is the same as that shown in the figure.

3. However, block read signals BLKRD2 and BLKRD3 are shown in FIGS. 8(h) and (i). PINV'L in continuation <(q) is an invalidation request signal, which is a signal that specifies data registered in the cache memory 24 and requests that it be invalidated. This invalidation request message'
The number P I N V L is generated by the monitoring directory 211 of the MM interface controller t 21 and sent to the memory access control circuit 30 .

Also, the INVL of the following (r) is, as explained earlier,
This is an invalidation signal that invalidates data registered in the cache memory 24. When this invalidation signal is received, an invalidation flag (not shown) is set in the area corresponding to the invalidation target data area in the directory memory 22. Can be erected.

Data D■-4 of memory access request signal MRQ■ is transferred at τ8. If the memory access request signal MRQ■ is to be transferred in the next τ1□ cycle, the memory access control circuit 30 sets the transfer period of the second word data D■-2 of the bronze read to As shown, when the cleat signal BLKRD2 is turned on at τ, the next τ,. The next τ1. which is one cycle later than τ1. Set stage transition inhibition signal 5TINH to 0 (off) in cycles.
(Figure 9 (1)).

As a result, the first stage 5TG1■, which is a stage process related to the memory access request signal MRQ■, performs τ1. Cache memory 2 continues to remain on until the cycle.
A valid hit determination is made at τ, 2 when the hit determination for 4 becomes possible, and the second stage 5TG2■ is normally executed in the τI2 cycle (Figure 8 (b),
e) , (j> , (goods)).

In the τlt cycle, as in the case of the τ3 cycle described above, the second cycle processing (second stage 5TG2) for the memory access request signal MRQ■ and the first cycle processing (second stage 5TG2) for the next memory access request signal MRQ■ are performed. 1 stage 5 TGI ■) is carried out in parallel (Fig. 8 (d)
), (e), (j), (k)).

However, if the main memory area registered in the directory memory 22 of the own cache memory 24 is written by another processor or DMA before the τ1□ cycle in which the data transfer for the memory access request signal MRQ■ is performed. If this occurs, the monitoring directory 211 generates an invalidation request signal PINVL at τ1° and sends it to the memory access control circuit 30.

Since the invalidation request must always be given priority over stage processing, the memory access control circuit 30
Upon receiving the invalidation request signal PINVL, the invalidation signal IN is activated in the next τ, I cycle.
VL is generated and the directory memory 22 is invalidated.

Therefore, the processor 26 receives the first stage 5TG of the memory access request signal MRQ■ in the τ11 cycle.
Processing I■ becomes impossible to execute. As a result, it becomes impossible to perform hit determination on the candidate memory 24, and subsequent processes also become impossible.

Therefore, even if such an invalidation occurs,
In order to allow the previous stage processing to be executed normally after performing the invalidation processing on the xenosh memory 24 and the directory memory 22, conventional memory access control performs the following steps as explained in FIG.
τ when the transfer of data D■-1 to ■ at the time of mishit is completed
Stage transition inhibit signal 5 from the next τ1□ cycle of 11
TINH is turned off and stage processing is restarted.

With this, if,τ,. Even if the invalidation request signal PINVL is generated in a cycle, a predetermined invalidation process is performed on the directory memory 22 in the next τ cycle, and from the following τ1□ cycle onwards, as explained earlier in FIG. Each stage of processing up to this point is executed successfully.

Note that the hit delay signal HIT shown in (2) in FIG.
D is a signal obtained by delaying the hit signal HIT by one cycle, and the first stage valid signal 5TG1■ is a signal indicating that the first stage processing is valid. Both signals are generated inside the memory access control circuit 30,
Among these, the stage 1 valid signal 5TGIV and the hit delay signal HITD are the stage transition inhibit signal ST I
It is used to generate NH.

[Problems to be Solved by the Invention] As mentioned above, in conventional memory access control, when a cache memory miss occurs, invalidation of the cache memory occurs when reading and transferring the missed data from the main memory. However, in order to ensure that memory access control and stage control can be executed normally, stage processing is restarted one cycle after the cycle in which mishit data transfer is completed.

For this reason, even though the probability of invalidation occurring when a cache memory miss occurs is usually low, an extra cycle is always inserted when a cache memory miss occurs, resulting in subsequent processing being delayed by that amount and reducing the overall memory capacity. There was a problem that access processing efficiency decreased.

The present invention improves memory access processing efficiency by delaying the start cycle of stage processing, which is resumed after the data transfer of the missed data is resumed only when invalidation occurs, when a cache memory miss occurs. The purpose of the present invention is to provide a memory access control circuit with improved performance.

[Means for solving the problems] The means adopted by the present invention to solve the above-mentioned problems are as follows:
This will be explained with reference to FIG. FIG. 1 shows the basic configuration of the present invention in blocks.

In FIG. 1, 10 is the entire memory access control circuit, which sends out an address in the first cycle, transfers data in the second cycle by overlapping with the first cycle of the next access, and in the first cycle The sent address and the hit information and hit block number information obtained by accessing the tag memory using the address are held during the second cycle, and if the hit information indicates a hit, the held address is stored in the second cycle. A cache memory (not shown) is accessed using the block number and address, and if there is a miss, the block is read from the main storage using the address and the cache memory is accessed in two cycles.

11 is a stage transition inhibition signal generation circuit (hereinafter referred to as 5TIN
H generation circuit), and a stage transition suppression signal ST that suppresses stage transition in the second cycle when the hit information output in the first cycle indicates a miss.
Perform processing to generate I NH.

12 is a memory access request permission signal generation circuit (hereinafter referred to as M
(represented by the RQOK generation circuit), and when a miss occurs, the memory access request permission signal MRQOK (represented by the MRQOK signal) is turned off, and in the cycle immediately before the last data read from the main storage at the address reaches the cache memory. Processing is performed to turn the MRQOK signal from off to on. The MRQOK signal is as described above.

Reference numeral 13 denotes a stage transition inhibition stop circuit (hereinafter referred to as 5TINH stop circuit), which detects that the MRQOK signal' is turned on from off, and turns on the 5TINH generation circuit 1.
Processing is performed to stop the stage transition inhibition signal 5TINH generated by 1.

14 is a memory access request permission suppression circuit (hereinafter referred to as MRQ).
(shown as an OK suppression circuit), and when a request to invalidate the own cache memory is made in a cycle in which the MRQOK signal is turned on, the MRQOK generation circuit 12 generates an MR signal in order to perform invalidation processing in the cycle.
Performs processing to prevent the QOK signal from turning on.

[For production]

The effects of the present invention are as follows: (1) When there is a hit in the cache memory, (2) When there is a miss on the cache memory and there is no invalidation request, and (3) When there is a miss on the cache memory and there is no invalidation request. Each case will be explained separately.

(1) When the cache memory is hit During normal operation when the cache memory is hit, the memory access control circuit 10 performs memory access control in two cycles.

That is, in the first cycle, an address for accessing the main memory (not shown) is sent, and in the second cycle, data is transferred from the main memory by overlapping with the first cycle of the next access.

The directory memory is accessed using the address sent in the first cycle and the address, and the obtained hit information and address information (for example, hit block number information) are held during the second cycle.

If the hit information indicates a hit to the cache memory, the cache memory (not shown) is accessed in the second cycle using the held address information to read predetermined data.

Thereafter, for each access, the aforementioned two-cycle memory access control is repeated in such a way that the second cycle (data transfer stage) of the current access and the first cycle (address sending stage) of the next access overlap. .

(2) When there is a miss in the cache memory and there is no invalidation request, the 5TINH generation circuit 11 suppresses stage transition in the second cycle when the hit information output in the first cycle indicates a miss. Signal 5TI
NH is generated to prevent transition of stage processing performed by a processor (not shown) in the second cycle.

On the other hand, the MRQOK generation circuit 12 generates MR
With the QOK signal turned off, the memory access control surface 110
interrupts memory access control.

While the memory access control in the memory access control circuit 10 is suspended, the processor performs a process of reading mishit data from the main memory in block units, for example, based on the address information.

The MRQOK generation circuit 12 turns the MRQOK signal from off to on in a cycle immediately before the last read data reaches the cache memory.

The 5TINH stop circuit 13 detects that the MRQOK signal generated by the MRQOK generation circuit 12 is turned on from off, and stops the stage transition inhibit signal 5TINH generated by the 5TINH generation circuit 110.

As a result, the first cycle of the next access is executed immediately from the cycle following the cycle in which block reading of the mishit data from the main memory is completed.

In this way, if there is a miss in the cache memory but there is no invalidation request, when reading of the missed data from the main memory is completed, the next access is immediately started without waiting for the next cycle as in the conventional method. Since one cycle of processing is executed, there are no wasted cycles, and memory access processing efficiency can be improved.

(3) When there is a cache memory mishit and an invalidation request If there is a cache memory mishit and an invalidation request is generated for the cassonry memory when reading and transferring the mishit data from the main memory, that is, the MRQOK signal If a request to invalidate its own cache memory is made in a cycle in which the MRQOK generation circuit 12 is turned on again, the MRQOK suppression circuit 14 of the memory access control circuit 10 generates the MRQOK generation circuit 12 in order to perform invalidation processing in the cycle. MRQ OK
Performs processing to prevent the signal from turning on.

As a result, in the cycle following the cycle in which block reading of mishit data from the main memory is completed, the processing of the first cycle of the next access is suppressed.
Invalidation processing is performed regarding the cache memory area targeted for invalidation.

When the invalidation process is completed, the process for the next access is normally executed from the next cycle.

In this way, only when there is a mishit in the cache memory but an invalidation request is made, when the block read of the missed data from the main memory is completed, the next cycle is opened like in the conventional method and the invalidation is performed. Processing will take place.

Note that in the case of DMA transfer, invalidation requests may occur continuously, but in that case, the MRQOK generation circuit 12
Processing is performed to prevent the MRQOK signal generated by the MRQOK signal from turning on.

As a result, cycles for performing invalidation processing are inserted in accordance with the number of invalidation requests, and invalidation processing for successive invalidation requests can be performed normally.

As described above, in the case of a cache memory mishit, the stage processing is restarted with a one-cycle delay after data transfer of the mishit data is completed only when an invalidation request occurs. When there is no wasted cycles, memory access processing efficiency can be improved.

In addition, stage processing is restarted after a delay of the number of cycles corresponding to the number of invalidation requests, so even if invalidation requests occur consecutively, these invalidation processes can be processed normally and are not interrupted. The stage processing for each access request can be restarted normally.

[Embodiment] An embodiment of the present invention will be described with reference to FIGS. 2 to 6. FIG. 2 is an explanatory diagram of the configuration of a memory access control system in which a memory access control circuit according to an embodiment of the present invention is used, FIG. 3 is an explanatory diagram of the configuration of an embodiment of the present invention, and FIG. FIG. 5 is an operation timing chart when there is no invalidation request in the embodiment, and FIG. 5 is an operation timing chart when there is an invalidation request in the same embodiment. The stage transition explanatory diagram of FIG. 6 is as described above.

(A) Configuration of Embodiment In FIG. 2, the configuration other than the memory access control circuit 10 is the same as the configuration of the conventional memory access control system explained in FIG. will be explained using the same reference numerals.

That is, 21 is a main memory interface controller (MM interface controller), which performs interface control between the main memory and a memory access control circuit (not shown). 211 is a monitoring directory provided in the MM Zeinface controller 21;
It monitors writes by other processors or DMA (direct memory access) to the main memory area registered in the directory of its cache.

MAR is an address bus between the MM interface controller 21 and the main memory, and MAD is a data bus between the MM interface controller 21 and the main memory.

22 is a directory memory in which address information of data registered in the cache memory and information indicating whether the data is valid or invalid are registered.

HIT is a hit signal indicating that the cache memory 24 has been hit, and indicates 1 when there is a hit, and indicates 0 when there is a miss.

23 is a hit number holding register (indicated by HIT register), in which hit information read from the directory memory 22 in the first cycle is stored.

A cache memory 24 is composed of high-speed memory elements such as bipolar transistors, and temporarily registers accessed data in the main memory.

A cache address holding register (cMA register) 25 stores an address for accessing the cache memory 24 sent out in the first cycle and holds it until the next second cycle.

A processor 26 executes stage processing in each cycle and controls the operation of the entire system.

261 is an address register provided in the processor 26, in which addresses for accessing the main memory, directory memory 22, and cache memory 24 are stored.

262 is a data register provided in the processor 26, in which data read from the cache memory 24 or main memory is stored.

AB is an address bus between the MM interface controller 21 and the processor 26, CB is a control signal bus to which various control signals are transferred, and DB is a data bus to transfer data between the MM interface controller 21 and the processor 26. It is.

INVL is an invalidation signal that invalidates data registered in the cache memory 24. When this invalidation signal is received, an invalidation flag (not shown in the figure) is set in the area corresponding to the invalidation target data area in the directory memory 22. ) will be erected.

The memory access control circuit IO is provided in the MM interface controller 21 and receives instructions from the processor 26 to control memory access to the main memory. The operation of the memory access control circuit 10 is performed in synchronization with the clock CLKO.
is generated in synchronization with the system clock 5CLK.

Furthermore, the various control signals generated by this memory access control circuit IO are the same as those explained in the operation timing charts of the conventional memory access control circuit in FIGS. 8 and 9, but the following memory access control circuit Also in the section of the configuration of one embodiment, explanations will be given as necessary.

Next, with reference to FIG. 3, the configuration of one embodiment of the memory access control circuit of the present invention will be described.

In FIG. 3, the 5TINH generation circuit ILMRQOK generation circuit 12, the 5TINH stop circuit 13, and the MRQOK suppression circuit 14 are as described in FIG.

The 5TINH generation circuit 11 includes an AND circuit 111 and a JK
It is composed of a flip-flop (hereinafter referred to as JKFF) 112. The AND circuit 111 receives the AND output of the first stage signal 5TG1, the *HITD signal, and the 5TGIV signal, which will be explained later, and outputs the AND output from the JKFF11.
Input to the J terminal of 2.

JKFF112 operates in synchronization with the clock CLKO which is synchronized with the system clock, and the MRQO
The MRQOK stop signal from the K suppression circuit 14 is input,
A stage transition inhibition signal ST I NH is output from the output terminal Q.
is generated, and an inverted stage transition inhibit signal *5TINH is generated from the inverted output terminal.

The MRQOK generation circuit 12 includes an inverter 121 and an AND
It is composed of a circuit 122 and a JKFF 123.

The hit signal HIT inverted by the inverter 121 and the first stage signal 5TG1 are input to the +1ND circuit 122, and the AND output thereof is input to the J terminal of the JKFF 123.

JKFF123 operates in synchronization with clock CLK1, which will be explained later, and a block read signal BLKRD2 instructing to read the second block is input to its terminal.
MRQOK is connected to the inverted output terminal. A signal is generated. MRQOK, signal is block read signal B of K terminal
It becomes 1 (ON) when LKRD2 becomes 1 (ON), and becomes 0 (ON) when the input of the j terminal becomes 1 (ON).
off).

The 5TINH stop circuit 13 includes a D flip-flop (hereinafter referred to as DFF) 131 and an AND circuit 132.

A memory access request permission signal MRQOK is input to the D4 child of the DFF 1 31. The AND circuit 132 receives the inverted output terminal of the DFF 131 and the memory access request permission signal MRQOK, and its ant output is input to the 5TINH generation circuit 112. With this configuration, the 5TINH stop circuit 13
It is detected that the M'RQOK signal from the suppression circuit 14 is turned on from off, and a stage transition suppression stop signal (hereinafter referred to as
5TINH stop signal).

The MRQOK suppression circuit 14 is an inverter 141 and an AND
It is composed of a circuit 142. The AND circuit 142 includes MR
MRQOK from JKFF123 of QOK generation circuit 12
, and the invalidation request signal PINV inverted by the inverter 141 are input, and when the invalidation request signal PINV is O (off), the MRQO
A K signal is output.

Next, 15 is a stage signal generation circuit, which includes an AND-OR circuit 151, a DFF 152, an AND circuit 153, and a DF
It is composed of an F154, an AND circuit 155, and a DFF156.

AND OR circuit 151 includes AND circuits 151a, 15
1b and an OR circuit 151C. Quiet circuit 15
The MRQOK signal from the MRQOK suppression circuit 14 and the inverted stage transition suppression signal *ST I NH from the 5TINH generation circuit 11 are input to 1a, and the AND circuit 152
The stage transition inhibiting signal ST I NH from the 5TINH generation circuit 11 and the first stage signal 5TGI from the DFF 152 are input to b. The OR circuit 151C is
AND outputs from AND circuits 151a and 151b are input.

The DFF 152 operates in synchronization with the clock CLKI, and the OR circuit 15 of the AND OR circuit 151 is connected to its D terminal.
The OR output of 1c is input, and the first
A stage signal 5TG1 is generated.

The Q terminal output 5TGI from the DFF 152 and the inversion stage transition inhibition signal *ST I NH from the 5TINH generation circuit 11 are input to the AND circuit 153 .

The DFF 154 operates in synchronization with the clock CLKI, the AND output of the AND circuit 153 is input to its D terminal, and the second stage signal 5TG2 is generated from its output terminal Q.

The first stage signal 5TG1 from the DFF 152 and the inverted stage transition inhibition signal *5TINH from the 5TINH generation circuit 11 are input to the AND circuit 155.

DFF 156 operates in synchronization with clock CLKO,
The AND output of the AND circuit 155 is input to the D terminal, and the first stage valid signal 5T is output from the output terminal Q.
Generates GIV.

16 is an HrTD generation circuit, which includes DFF161 and AN
It is composed of a D circuit 162.

The DFF161 operates in synchronization with the clock CLKI, the hit signal HIT is input to its D terminal, and the hit signal HIT is input to the clock CLKI from its inverted output terminal.
An inverted delayed hit signal *HITD, which is an inverted signal of the delayed hit signal HTTD, which is delayed by one cycle of the delayed hit signal *HITD, is generated.

The AND circuit 162 receives the inverted delayed hit signal *HrTD from the DFF 161 and the first stage valid signal 5TGIV from the DFF 156, and when both the inverted delayed hit signal *HITD and the first stage valid signal 5TGIV are on, , outputs an inverted delayed hit signal *HITDV.

F is a clock inhibition generation circuit, and inverter 171
, an AND circuit 172, and a JKFF 173.

The AND circuit 171 receives the hit signal *HIT inverted by the inverter 171, the inverted stage transition suppression signal *s'rrNH from the 5TINH generation circuit 11, and the DFF1.
The first stage signal 5T (1, 1) from 52 is input, and the AND output thereof is input to the J terminal of the JKFF 173.

JKFF173 operates in synchronization with clock CLKO,
The start signal 5TART is input to that terminal, and the clock suppression signal CLKS is output from its inverted output terminal *Q.
An inverted clock suppression signal *CLKSP which is an inverted signal of P
is output.

18 is a clock generation control circuit, AND @route 18
1 and controls the generation of the clock CLKI. That is, the ND circuit 181 receives the inverted clock suppression signal *C from the JKFF 173 of the clock suppression generation circuit 17.
When LKSP and clock CLKO are input and the inverted clock suppression signal *CLKSP is 1 (on), that is, during normal operation when the clock suppression signal CLKSP is off,
Clock CLKO is output as clock CLKI.

The operation of the memory access control circuit 10 described above will be explained in the section describing the operation of the next embodiment.

(B) Operation of the Embodiment The operation of the embodiment will be explained with reference to the operation timing charts of FIGS. 4 and 5 and the stage transition diagram of FIG. 6.

In the embodiment of the present invention as well, two-cycle memory access control is performed according to the stage transition shown in FIG. 6, but FIG. 6 is as described above.

First, the memory access control operations common to the above (1) to (3) will be explained with reference to the operation timing chart of FIG. In FIG. 4, the clock CLKI is generated by the clock generation circuit 18 into a clock CLK (not shown).
Generated in synchronization with O. τ1, τ2, etc. are clock C
Each cycle of LKO is shown (FIG. 4(a)). The clock CLKO is a clock generated in synchronization with the system clock 5CLK as described above, and defines the timing of each operation performed within the memory access control circuit 10.

When accessing the main memory (not shown), the processor 26 sends out a memory access request signal MRQ in the memory request stage shown in FIG. 6 (FIG. 4(b)). Now, memory access requests MRQ are generated successively in cycles τ1, τ2, and τ3 of clock CLKO, and these are designated as memory access request signals MRQ■, MRQ■, and MRQ■ as shown in the figure (4th output). ).

In response to the first memory access request signal MRQ issued in τ1 cycle, a memory access request permission signal M is issued in the same τ cycle to permit the memory access request.
RQOK (indicated by the MRQOK signal) is received and notified to the memory access control circuit (FIG. 4(c)).

The DFF 152 of the memory access control circuit 10
Upon receiving the RQOK signal, the first stage signal 5TGI is activated in the next cycle τ2 in synchronization with the clock CLK1.
STGI (indicated by ■) is generated and sent to the processor 26 via the control signal bus CB (■ in FIG. 4(b)).

Upon receiving this first stage signal 5TGI, the processor 26 performs the first stage processing in the second cycle τ2, and sends out the address for accessing the main memory in the address register 251 via the address bus AB. In (2) of Figure 1), a hit determination for the cache memory is also performed.

That is, the address sent by the processor 26 first accesses the directory memory 22.

When the address corresponding to the address to be accessed exists in the directory memory 22, the hit signal HIT becomes 1, indicating that the cache memory has been hit. If the address corresponding to the accessed address does not exist in the directory memory 22, the hit signal HIT becomes 0, indicating that there has been a miss in the cache memory.

This hit signal HIT is sent to the memory access control circuit 10 via the MM interface controller 21.

Further, hit information of the cache memory is stored in the HIT register 23. The hit information in the HIT register 23 is sent to the cache memory 24, and when the hit signal HIT is 1 (hit in the cache memory), the area of the cache memory 24 corresponding to the hit bronch number S of the directory memory 22 is selected. be done.

The operation of the example is described below: (1) When there is a hit in the cache memory, (2) When there is a miss on the cache memory and there is no invalidation request, and (3) When there is a miss on the cache memory and there is no invalidation request. We will explain the cases in which there is.

(1) When the cache memory is hit During normal operation when the cache memory is hit, the memory access control circuit 10 performs memory access control in two cycles.

When there is a hit in the cache memory 24, that is, when the hit signal HIT is 1, the memory access control circuit 1
The DFF 154 of 0 outputs the second stage signal 5TG2 (
STGI (indicated by ■) is generated and sent to the processor 26 (
■ in Figure 4(e)).

Upon receiving this first stage signal 5TGI■, the processor 26 performs the first two stage processing in the second cycle τ3, reads out the hit data from the cache memory 24, and transfers it to the data register 262 via the data bus DB. do.

On the other hand, in this cycle τ3, the processing of the second cycle (second stage) for the first memory access request signal MRQ■ overlaps with the processing of the first cycle (first stage) for the next memory access request signal MRQ■. Processing is performed (see 5TGI■ in FIG. 4(d) and 5TG2■ in FIG. 4(e)).

The first cycle of the next memory access request signal MRQ■ (
The first stage 5TG1 of the τ3 cycle in Fig. 4(d)
), when the cache memory 24 is hit, the memory access request signal MR is activated in the following τ4 cycle.
The second cycle of Q■, that is, the second stage 5TG2
Processing (2) is executed.

Similarly, when the cache memory is hit, each process of the first stage 5TGI and second stage 5TG2 is executed successively for each memory access request signal MRQ (not shown).

(2) If there is a miss in the cache memory and there is no invalidation, the memory access request signal MRQ made at τ2 is now
In the processing of the first stage 5TGI■, if the address sent from the processor 26 misses the cache memory 24, the hit signal BIT becomes O in cycle τ2 (FIG. 4 (e)), and the HIT register 23 is stored in

Clock inhibition generation circuit 1 of memory access control circuit 10
7, when the hit signal HIT is 0 (miss hit),
In the τ3 cycle, the DFF 173 generates a clock inhibit signal *CLKSP (an inverted signal of cLKSP).

On the other hand, when the hit signal HIT is 0 (miss) and the first stage 5TGl■ of the continuous memory access request signal MRQ■ is on, the 5TINH generation circuit 11 generates a τ3 cycle in FIG. ), JKFF11
The stage transition inhibiting signal 5TINH outputted by No. 2 is turned on for τ4 cycles (FIG. 4(p)).

As a result, [FF15 of the memory access control circuit 10
The value number of the first stage signal STC, 1■ of the memory access request number MRQ■ generated from 2: τ, starts to hold the value 1 continuously after the cycle (Fig. 4(d)).
, generated from DFF l 52 t.

The second stage signal 5TG2■ of the memory access request signal MRQ■ continues to hold the value 1 after the τ3 cycle (FIG. 4(e)).

Also, as mentioned above, in the τ3 cycle, the DFF173
The inverted clock suppression signal *CLKSP generated by *CLKSP is turned off (
When the clock inhibit signal CLKSP turns on), the clock generation circuit 18 is inhibited from generating a clock CLKI with a threshold of τ4 or more, and the control operation of the memory access control circuit IO from the τ4 cycle onwards is interrupted at - time (the fourth Figures (r) and (a)).

While the control operation of the memory access control circuit 10 is temporarily suspended due to a miss in the cache memory 24, the MM interface controller 21 retrieves the missed data from the main memory (not shown) and transfers the data to the data bus D). Prosensor 2 via B
6, this read data is registered in the cache memory 24, and the tag information such as its address is registered in the directory memory 21. This data transfer □ process is performed during cycles τ4 to τ.

Data reading from the main memory is performed in block units, and multiple words (in the figure, D■-1 to D
-4 word) is read and transferred to the processor 26 and cache memory 24 (FIG. 4 (9)).

When data in each block is read, block read signals BLKRDI to BLKRD4 are sent from the MM interface controller 21 to the memory access control circuit 10. Read signals BLKRD2 and BLKRD3 are shown.

When the first data D■-1 is transferred, the processor 2
6 can move on to the next process, so the memory access control circuit 1
The suppression of the 0 clock CLK may be stopped and its control resumed. Therefore, MM Zein Face Controller 21
sets the start signal 5TART to 1 (on) (the fourth
τ in Figure (S)).

When the start signal 5TART becomes 1, the JKFF 173 of the clock inhibition generation circuit 17 generates the next τ.

Turn on the inverted clock inhibit signal *CLKSP in the cycle (
(turn off the clock suppression signal CLKSP).

When the inverted clock inhibit signal *CLKSP is turned on, the clock generation circuit 18 restarts generation of the clock CLKI in synchronization with the clock CLKO (the cycle τ in FIGS. 4(a) and 4(r)).

In this embodiment, in accordance with the gist of the present invention, when there is no invalidation, the stage Stop transition suppression,
Stage transition starts from the next τ, 2 cycles.

That is, when the block read signal BLKRD2 for block 2 becomes 1 (on) in cycle τ, JKFF123 of the MRQOK generation circuit 12 outputs MRQOK.
Change the signal from 0 to 1 (off to on). When there is no invalidation request, invalidation request signal PI
Since NV is O, the MRQOK suppression circuit 14
M from JKFF123 without suppressing the OK signal
The RQOK signal is output as is and turned on from off (τ, .cycle in FIG. 4(b)).

The 5TINH stop circuit 13 detects that the MRQOK signal from the MRQOK suppression circuit 14 is turned on from off, and outputs the 5TINH stop signal to the terminal of JKFFl12.

When the 5TINH stop signal is stopped, the 5TINH generation circuit 112 turns off the stage transition inhibiting signal 5TINI (*5TINH is turned on) (τ11 cycle of Φ in FIG. 4).

As a result, the first stage 5TG1■, which is a stage process related to the memory access request signal MRQ■, performs τ1. Cache memory 2 continues to remain on until the cycle.
A valid hit determination is made at τ, when the hit determination for 4 becomes possible, and the second stage 5TG2■ is normally executed in the τ1□ cycle (Fig. 4(d), (
e), (b)).

In the τ1□ cycle, as in the case of the τ3 cycle described above, the second cycle processing for the memory access request signal MRQ■ (second stage 5TG2■) and the first cycle processing for the next memory access request signal MRQ■ ( The first stage 5TGI■) is carried out in parallel (Fig. 4(d)
), (e), (m), (n)).

As described above, a miss occurs in the cache memory,
If there is no invalidation request, the suspended processing of each stage is immediately resumed from the τ1□ cycle following the τ11 cycle in which the data transfer for the mishit data has been completed.

(3) When there is a cache memory miss and an invalidation request Memory access control when there is a cache memory miss and an invalidation request will be described with reference to FIG.

Figure 5 shows the operation timing chart as in the 4th time, (a) CLK ~ (s) S T A RT
(7) The meaning of each symbol and the operation contents up to the τ9 cycle are the same as the operation contents in FIG. 4.

Furthermore, as explained earlier, rNVL in (2) is an invalidation signal that invalidates the data registered in the cache memory 24, and when this invalidation signal is received, the invalidated data in the directory memory 22 is invalidated. An invalid flag (not shown) is set in an area corresponding to the target data area.

If a write is performed to the main memory area registered in the directory memory 22 of the own cache memory 24 by another processor or DMA one cycle τ before the data transfer for the memory access request signal MRQ■ is performed. For example, monitoring directory 2
11 generates an invalidation request signal PINVL and sends it to the memory access control circuit 10 in the τ1° cycle one cycle before the data transfer ends τ1.

Since the invalidation request must always be performed with priority over stage processing, M of the memory access control circuit 10
When the invalidation request signal P INVL becomes 1 (ON), the RQOK suppression circuit 14 blocks the MRQOK signal from the MRQOK generation circuit 12 and maintains the 0 (OFF) state (τ1° in FIG. 4(c)). cycle).

Therefore, from the 5TINH stop circuit 13, 5TINH
The stop signal is not stopped, and the 5TINH generation circuit 11 generates τ
Even in the 1° cycle, the stage transition inhibition signal 5 continues.
Generates TINH and inhibits stage transition.

If there is one invalidation request, the MRQOK suppression circuit 14 stops suppressing the MRQOK signal from the MRQOK generation circuit I2 in the cycle τ in which the invalidation request PINVL is turned off, and the MRQOK suppression circuit 14 stops suppressing the MRQOK signal from the MRQOK generation circuit I2.
Generate the K signal and turn it from off to on (Figure 4 (b)
τ11 cycles).

The 5TINH stop circuit 13 detects that the MRQOK signal from the MRQOK suppression circuit 14 has changed from off to on, outputs the 5TINH stop signal, and inputs it to the terminal of the JKFF 112.

Upon receiving this ST I NH stop signal, the 5TTNH circuit 11 turns off the stage transition inhibition signal 5TINH (
*5TINH is turned on) (τ1□ cycle in Figure 4 (p)).

As a result, the first stage 5TG1■, which is the stage processing related to the memory access request signal MRQ■, continues to maintain the on state until the τ1□ cycle, and the cache memory 2
An effective hit determination is made at the τth time when the hit determination for 4 becomes possible, and τ.

In the cycle, the second stage 5TG2■ is normally executed (FIG. 4(d), (e), (m)).

On the other hand, in the τ11 cycle, invalidation processing is performed on the invalidation target data in the directory memory 21 (τ cycle in FIG. 4(2)).

If, τ,. If multiple invalidation requests occur consecutively following an invalidation request in a cycle, the MRQOK suppression circuit 14 suppresses generation of the MRQOK signal for that period, and
continues to generate the stage transition inhibit signal 5TrNH.

In the cycle in which the invalidation request P rNVL is turned off, the MRQOK suppression circuit 14
The suppression of the signal is stopped, and in response to this, the 5TINH circuit 1
1 turns off the stage transition inhibition signal 5TINH (*5T
INH is on).

As a result, in the same way as described above, the processing of each stage that was interrupted at - is continued normally.

As described above, a miss occurs in the cache memory,
And only if there is an invalidation request, one cycle is opened next to the cycle in which the data transfer for the mishit data has finished, invalidation processing is performed, and from the next cycle, each interrupted data transfer is immediately resumed. Stage processing is resumed.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and various modifications can be made in accordance with the gist of the invention.

For example, the amount of data transferred when a cache memory miss occurs is not limited to 4 words. Further, as explained in the embodiments above, the present invention is applicable even when a plurality of invalidation requests are made in succession at the time of a mishit.

〔effect〕

As explained above, according to the present invention, the following effects can be obtained.

(1) When there is a miss in the cache memory, stage processing is restarted with a delay of 1 cycle after the data transfer of the miss data is completed only when an invalidation request occurs, so there is no wasted cycles when there is no invalidation request. As a result, memory access processing efficiency can be improved.

(2) If stage processing is restarted after a delay of the number of cycles corresponding to the number of invalidation requests, even if invalidation requests occur consecutively, these invalidation processes can be processed normally, and the interruption can be prevented. The stage processing for each access request made can be restarted normally.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the basic configuration of the present invention, FIG. 2 is an explanatory diagram of a memory access control system in which a memory access control circuit according to an embodiment of the present invention is used, and FIG. 3 is an explanatory diagram of an embodiment of the present invention. An explanatory diagram of the configuration of the example, FIG. 4 is an explanatory diagram of the operation timing chart of the same embodiment, FIG. 5 is an explanatory diagram of the operation timing chart of the same embodiment when there is a mishit and invalidation, and FIG. is an explanatory diagram of stage transition, FIG. 7 is an explanatory diagram of a conventional memory access control system, FIG. 8 is an explanatory diagram of an operation timing chart of a conventional memory access control system, and FIG. 9 is an explanatory diagram of a conventional memory access control system. FIG. 6 is an explanatory diagram of an operation timing chart when there is a mishit and invalidation. 1 and 2, 10... memory access control circuit, 11... stage transition inhibition generation circuit (STINH generation circuit), 12...
・Memory access request permission signal generation circuit (MRQOK generation circuit), 13... Stage transition suppression stop circuit (ST
IN) I stop circuit), 14...Memory access request permission suppression circuit (MRQOK suppression circuit).

Claims (3)

[Claims] (1) Send an address in the first cycle, perform data transfer in the second cycle by overlapping with the first cycle of the next access, and access the directory memory using the address sent in the first cycle and the address. The obtained hit information and address information are held for a second cycle, and if the hit information indicates a hit, the cache memory is accessed in the second cycle using the held address information, and if a miss occurs, In a memory access control circuit that reads data from the main memory based on the address information and accesses the cache memory in two cycles, (a) If the hit information output in the first cycle indicates a miss, the second cycle a stage transition inhibiting signal generation circuit (11) that generates a stage transition inhibiting signal to inhibit stage transitions; a memory access request permission signal generation circuit that turns on the memory access request permission signal from off in a cycle immediately before the last data reaches the cache memory;
12), and (c) detects that the memory access request permission signal is turned on from off, and activates the transition suppression signal generation circuit (11).
1. A memory access control circuit comprising: a stage transition inhibition stop circuit (13) for stopping a stage transition inhibition signal generated by ). (2) If a request to invalidate the own cache memory is made in the cycle in which the memory access request permission signal is turned on, the memory access request permission signal is turned on in order to perform the invalidation process in the cycle. 2. The memory access control circuit according to claim 1, further comprising a memory access request permission suppression circuit (14) for suppressing memory access requests. (3) In the cycle in which the access request permission suppression circuit (14) turns on the memory access request permission signal, if a request to invalidate the own cache memory is made consecutively, the memory access request will continue to be permitted for that period. 3. The memory access control circuit according to claim 2, wherein the memory access control circuit suppresses the signal and turns on the memory access request permission signal from a cycle in which invalidation is no longer necessary.