JPH0415677B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a clock regeneration circuit for correctly capturing data sent superimposed on a predetermined period of a video signal.

[Technical Background of the Invention] In recent years, in television broadcasting, etc., other data such as image information is superimposed and transmitted in a predetermined period within the vertical retrace period in addition to the video signal, and the receiving side receives the data. A device has been developed that displays image information and the like on a screen by taking out the data, writing it into a memory, and reading out the data written into the memory.

To retrieve the above data, the clock run section is removed using a sampling clock synchronized with the clock run, which is a synchronization signal sent prior to the data packet, and the data packet is retrieved. In this case, unless the sampling clock is synchronized with the clock run, data packets cannot be captured correctly.

FIG. 1 shows a conventional example of a clock regeneration circuit for regenerating the clock for taking in the data packet.

In the figure, in order to ensure digital synchronization on the receiver side and facilitate signal processing, the reference clock oscillator 1, which outputs a frequency 8sc that is eight times the color subcarrier frequency sc, is a counter circuit that divides the frequency by 5, etc. A sampling clock of 8/5sc is produced through the configured frequency divider 2. The phase comparison pulse of 8/5sc extracted from the frequency divider 2 and data obtained by waveform shaping the video signal on which information is superimposed (hereinafter abbreviated as slice data) are phase-compared by the phase comparator 3. . The comparison output is extracted (taken in) by the clock run gate circuit 4 for a period in the clock run portion of the slice data;
By the comparison output in this clock run section,
It is configured to control the phase of the sampling clock, which is the output of the frequency divider 2, in synchronization with the phase of the clock run of slice data.

By the clock run gate circuit 4, only the period in the clock run part of the slice data is
A gate pulse, which serves as a reference for passing the comparison output to the frequency divider 2 side, is generated under control to have an appropriate phase by an oscillator whose phase is synchronized with the horizontal synchronizing signal.

FIG. 2 is a circuit diagram showing a conventional example of the clock recovery circuit.

In the figure, reference numerals 11 to 18 are JK flip-flops (hereinafter abbreviated as FF);
FF11 to FF15 are each configured to be a 10 frequency divider that receives an 8sc clock as input. In other words, the output terminal Q and inverted output terminal of FF11 are connected to the input terminals J and K of FF12 in the next stage, respectively, and the output terminal Q and inverted output terminal of FF12 are further connected to the input terminals J and K of FF13 in the next stage, respectively. The FF15 is connected in the same way, and the output terminal Q and the inverted output terminal of the FF15 are connected to the input terminals J and K of the FF11, respectively.

Each input terminal J and K of FF18 and FF16 has
The output of FF18, which is connected to input terminals J and K of FF15, is in phase with FF15, and the output of FF16, which receives a clock whose phase is inverted from that of FF14, is delayed by 1/2 clock from FF14.

The output terminal Q and the inverted output terminal of this FF16 are FF
17 input terminals J and K, respectively, and FF
The output of FF17 has a phase further delayed by one clock from FF16. The output from each output terminal Q of the FF12 and FF16 (also simply referred to as output Q) is passed through an exclusive OR circuit 20 and used as a sampling clock.

On the other hand, a mono-multi vibrator (hereinafter referred to as mono-multi vibrator) is triggered by the horizontal oscillation output pulse H synchronized with the horizontal synchronization signal and becomes an oscillator that generates a clock run gate pulse with a predetermined pulse width by setting the values of the resistor and capacitor. ) 21 clock run gate output CR is input to 4-input NAND circuits 22 and 23, respectively. The slice data SD is input to these NAND circuits 22 and 23, the output Q of FF14 and the inverted output of FF16 are input to the NAND circuit 22, and the output Q of FF17 and the inverted output of FF18 are input to the NAND circuit 23.
The inverted output of is input.

The NAND circuit 22 outputs Q and FF of the FF14.
Since 16 inverted outputs are input, the output is normally 1 with respect to the rising phase of the output Q of FF15.
The NAND circuit 23 outputs a half-clock pulse in the phase before the clock, while the NAND circuit 23 outputs the output Q of the FF17.
By inputting the inverted output of FF18, the normal FF
It outputs a half-clock pulse with the same phase as the rise of output Q of No. 15.

The respective outputs of these NAND circuits 22 and 23 are passed through a 2-input AND circuit 24 to a preset terminal of the FF 15.
By applying the voltage to Pr, a divided output synchronized with the clock run portion of the slice data is generated, and a predetermined sampling clock for sampling the slice data is output.

The operation of the conventional example configured as described above will be explained with reference to the timing chart shown in FIG.

Now, as shown in Figure 3A, slice data
SR and clock run gate output CR are input to AND circuits 22 and 23, respectively, and from oscillator 1
FF whose 8sc clock pulse constitutes frequency divider 2
, terminals J and K of FF11 and FF11
The output waveforms of the output terminals Q of the FF18 to FF18 are represented by Q's Q1 to Q8 in the figure.

On the other hand, the waveform obtained by inverting the AND of the output Q of FF14 and the inverted output of FF16 is Q4 and Q6 in Figure 3A.
The waveform obtained by inverting the AND of the inverted output of FF18 and the output Q of FF17 is Q in A of the same figure.
8, Q7, so in the clock run (signal) section, the AND circuit 22 compares the phases of the rising waveform of the clock, and the AND circuit 23 compares the phases of the rising waveform of the clock. Therefore, if the phase is out of phase with the clock run section, the NAND circuits 22, 23
The AND circuit 24 outputs the logical product of the outputs of
By presetting FF15, the phase of the frequency-divided outputs of FF11 to FF15 is corrected.

The sample ring clock obtained in this way is shown in FIG. FIG. 3B shows waveforms of various parts at slightly different timing from that shown in FIG. 3A.

By the means described above, since the input clock has a period of 8 sc (that is, 35 n sec period), a phase correction of 35 n sec is performed by one preset, and therefore a 5-cycle clock run pulse signal is used. Phase correction will be completed.

This conventional means enables clock reproduction with a phase accuracy of ±35 nsec.

[Problems with background technology]

However, in the conventional clock regeneration means described above, the pulse of the clock run gate is directly triggered by the horizontal oscillator, so if the phase of the horizontal oscillator changes due to aging, aging, ambient temperature, weak electric field reception state, etc. The clock run gate pulse also fluctuated, making it impossible to accurately open and close the gate of the clock run section, making it impossible to regenerate the clock.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and provides a clock regeneration circuit for data signal acquisition that detects the start of a clock run and sets the period necessary for clock regeneration to enable accurate clock regeneration operation. The purpose is to provide.

[Summary of the invention]

The clock regeneration circuit for data signal acquisition of the present invention includes means for detecting the start of a clock run, means for counting clocks from the reference reference clock oscillation means during a period set as a clock regeneration period based on the detected signal, and a means for counting clocks from the reference reference clock oscillation means. The gate circuit includes means for outputting a clock run gate signal to open the gate for a period until the count value is reached.

[Embodiments of the invention]

Hereinafter, the present invention will be specifically explained with reference to FIG. 4 and subsequent figures.

FIG. 4 shows an embodiment of a gate signal generation circuit as a gate circuit for generating a clock run gate signal in a clock regeneration circuit for data signal acquisition of the present invention, and FIG. 5 shows a counter circuit used in FIG. shows.

In these figures, the gate signal generation circuit 31
The R-S flip-flop (R-SFF) 34 is formed of two-input NAND circuits 32 and 33 that detect the clock run section, and the output is sent to the clock enable terminal CE via the two-input NAND circuit 35.
is applied to the clock input end CK, for example, a counter circuit 36 starts counting 4/5sc clocks using the output Q from the FF 15 in the conventional example mentioned above as an input signal, and the output of this counter circuit 36 is set to the set value. It is comprised of a decoder circuit 37 which detects and outputs the set gate period for clock reproduction depending on whether the clock has reached or not.

One input end of the NAND circuit 32 is connected to a reset terminal (denoted as HR) to which a reset signal obtained by inverting the horizontal synchronization signal is input, and the other input end is connected to an output end of the NAND circuit 33. One input terminal of the NAND circuit 33 is a terminal into which the inverted slice data is input, and the other input terminal is connected to the output terminal of the NAND circuit 32.
-SFF34 is formed.

The output terminal of the NAND circuit 33 is connected to one input terminal of a two-input NAND circuit 35, and the NAND circuit 34
The input terminal of the counter circuit 36 is connected to the reset terminal R of the counter circuit 36.

The output of the counter circuit 36 is sent to the decoder circuit 3.
7 and is connected to the data input terminal of the decoder circuit 37.
The output terminal of is connected to the other input terminal of the NAND circuit 35 and serves as an output terminal 38 for the clock run gate signal.

The decoder circuit 37 is set, for example, to output a high level when the count value output input from the counter circuit 36 is from 0 to 4, and to output a low level when the count value output is 5 or more. There is.

The counter circuit 36 is a general binary counter, and is configured as shown in FIG. 5, for example.

That is, the 4/5sc clock signal is applied to one input terminal of the 2-input AND circuit 41, and the clock is output only when a low-level clock enable signal is applied to the other input terminal by passing it through the inverter circuit 42. It is designed to enable signal capture.

The output terminal of the AND circuit 41 is connected to each clock input terminal CK of the FFs 43 to 46, and each reset terminal R is connected in common to the reset terminal HR.

The output terminal Q _A of the D-type FF 43 in the first stage is connected to the terminals J and K of the J-KFF 44 in the second stage, and is also connected to each input terminal of 2-input and 3-input AND circuits 47 and 48, Inverting output terminal _A is connected to terminal D.

The output terminal Q _B of the FF 44 is connected to each input terminal of 2-input and 3-input AND circuits 47 and 48.
The output terminal of the input AND circuit 47 is the third stage FF4
The output terminal Q _C of the third stage FF45 is connected to the input terminal of a three-input AND circuit 48, and the output terminal of this AND circuit 48 is connected to the terminal J of the fourth stage FF46. , K, and these FF4
Each of the 3 to 46 output terminals Q _A to Q _D is connected to the data input terminal of the decoder circuit 37 .

The operation of the gate signal generating circuit 31 according to the present invention configured as described above will be explained with reference to the timing chart shown in FIG.

As shown in Figure 6a, the reset terminal HR has
The counter circuit 36 and R-SFF 34 are reset because a reset signal (indicated by ) is applied before the clock run portion of the data packet. This R-SFF34 is inverted slice data
It is reset at the falling edge of SD, that is, at the beginning of the clock run of the slice data as shown in FIG. 6b, and transitions to a high level as shown in FIG. 6c.

On the other hand, when the counter circuit 36 is also reset by the reset signal, the clock run gate output CR, which is the output of the decoder circuit 37, becomes high level as shown in FIG. 6d. NAND circuit 3 where output and input are input
5, when the R-SFF 34 becomes high level, a low level signal is applied to the counter enable terminal of the counter circuit 36 as shown in FIG. The counting operation of the clock signal shown is started.

When the count value of the counter circuit 36 advances and reaches a predetermined count value, that is, the period required for clock reproduction, the output of the decoder circuit 37 becomes low level, and at the same time, the clock enable terminal becomes high level, so that the counter circuit 36 stops the counting operation. The signal shown in FIG. 6e is used as a clock run gate signal, and the clock run is extracted during this gate signal period. By generating a sampling clock synchronized with the extracted clock run, it becomes possible to reproduce the data acquisition clock.

During the clock gate period set in this way, the phase of the clock signal 4/5sc input to the gate signal generation circuit 31 is gradually changed (sent) to the clock run unit by clock regeneration which is corrected by phase comparison. Since the gate signal generation circuit 3 is corrected so that it is synchronized with the phase of the clock of
The clock run gate period outputted from the clock run gate output terminal 38 of No. 1 is accurately set in the clock run section.

Therefore, by sampling data packets using this gate signal generation circuit 31, accurate data can be extracted in synchronization with the sent signal. In addition, the counter circuit 36 is a reference clock.
Since it counts 4/5sc, which is the frequency of 8sc, it does not count noise, making it extremely stable, and has the advantage of making the gate signal period accurate.

Note that in the above configuration, the decoder circuit 37
can also be constructed using a comparator. Further, it goes without saying that the counter circuit 36 is not limited to the circuit example shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, the clock run gate signal generation means for detecting the start portion of the clock run portion of the data packet signal and setting the period necessary for clock regeneration is provided, so that the configuration is relatively simple. Therefore, it is possible to reproduce the clock that is accurately synchronized with the clock run section and to accurately capture successive input data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a clock regeneration circuit, FIG. 2 is a circuit diagram showing a conventional clock regeneration circuit, and FIGS. 4 is a circuit diagram showing an example of the gate signal generation circuit according to the present invention; FIG. 5 is a circuit diagram showing an example of the counter circuit in FIG. 4; FIG. 6 is a circuit diagram showing an example of the counter circuit in FIG. FIG. 3 is a timing chart showing waveforms of various parts for explaining the operation shown in the figure. 1... Oscillator, 2... Frequency divider, 3... Phase comparator, 4... Gate circuit, 31... Gate signal generation circuit, 32, 33, 35... NAND circuit, 36...
...Counter circuit, 37...Decoder circuit.

Claims (1)

[Scope of Claims] 1. A circuit for regenerating a clock for capturing the data signal from a video signal in which a clock run signal and a data signal are superimposed for a predetermined period, the circuit comprising: a first clock signal representing the start of the clock run signal; a first means for generating a signal; a reference clock oscillation means for oscillating a reference clock; and a first means for supplying the first signal and the reference clock and starting a counting operation of the reference clock by the first signal. , comprising a counter circuit that performs a counting operation until a preset count value is reached, and a second means that generates a clock run gate signal for a period determined by the counting operation, and utilizes the clock run gate signal. 1. A clock regeneration circuit for taking in a data signal, wherein a clock run signal is extracted from the data signal, and a sampling clock is generated in synchronization with the extracted clock run signal.