JPH0415860U - - Google Patents
Info
- Publication number
- JPH0415860U JPH0415860U JP5665590U JP5665590U JPH0415860U JP H0415860 U JPH0415860 U JP H0415860U JP 5665590 U JP5665590 U JP 5665590U JP 5665590 U JP5665590 U JP 5665590U JP H0415860 U JPH0415860 U JP H0415860U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- oxide film
- semiconductor
- region
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図は、本考案の半導体装置の平面図、第２
図は第１図の要部斜視図、第３図は出力バツフア
ー回路を示す図、第４図は従来の半導体装置の平
面図、第５図は第４図の要部斜視図である。
FIG. 1 is a plan view of the semiconductor device of the present invention, and FIG.
1, FIG. 3 is a diagram showing an output buffer circuit, FIG. 4 is a plan view of a conventional semiconductor device, and FIG. 5 is a perspective view of the essential portion of FIG. 4.
Claims (1)
第２のトランジスタが第１の電源と第２の電源間
に設けられ、この第１のトランジスタと第２のト
ランジスタの接続点から出力する回路を有する半
導体装置であつて、 前記第１のトランジスタおよび前記第２のトラ
ンジスタのゲートは半導体基板内に形成されたＬ
ＯＣＯＳ酸化膜上からこのＬＯＣＯＳ酸化膜で囲
まれた素子領域へ延在され、且つこの素子領域で
曲折されて設けられ、 前記素子領域と前記ＬＯＣＯＳ酸化膜の境界お
よびその近傍を含んだ領域と前記曲折領域に形成
されたゲートを他のゲートよりも太く形成する事
を特徴とした半導体装置。 (2) 前記回路は出力バツフアー回路である事を
特徴とした請求項第１項記載の半導体装置。 (3) 複数のチツプ、ＣＰＵ、デコーダおよびこ
れらをつなぐ信号線とがあり、前記ＣＰＵからデ
コーダを介して入力される信号により、前記複数
の半導体チツプの中の１つが選択され、この選択
された半導体チツプの出力信号が前記ＣＰＵに入
力されて処理される回路の中で、 前記半導体チツプは、このチツプの周辺に出力
バツフアー回路を有し、このバツフアー回路の先
端に取りつけられたトランジスタは、半導体基板
内に形成されたＬＯＣＯＳ酸化膜に囲まれた素子
領域内に形成され、 前記トランジスタのゲートは、リーク電流を防
ぐために、ＬＯＣＯＳ酸化膜と素子領域の境界お
よびその近傍や曲折領域のみ太く形成される事を
特徴とした半導体装置。[Claims for Utility Model Registration] (1) A first transistor and a second transistor connected in series are provided between a first power source and a second power source; A semiconductor device having a circuit that outputs from a connection point, wherein gates of the first transistor and the second transistor are connected to an L formed in a semiconductor substrate.
A region extending from above the OCOS oxide film to a device region surrounded by the LOCOS oxide film and being bent in the device region, and including a boundary between the device region and the LOCOS oxide film and its vicinity; A semiconductor device characterized in that a gate formed in a bent region is formed thicker than other gates. (2) The semiconductor device according to claim 1, wherein the circuit is an output buffer circuit. (3) There are a plurality of chips, a CPU, a decoder, and a signal line connecting them, and one of the plurality of semiconductor chips is selected by a signal input from the CPU via the decoder, and the selected In a circuit in which an output signal of a semiconductor chip is input to the CPU and processed, the semiconductor chip has an output buffer circuit around the chip, and a transistor attached to the tip of the buffer circuit is a semiconductor chip. The gate of the transistor is formed in a device region surrounded by a LOCOS oxide film formed in the substrate, and the gate of the transistor is formed thick only at the boundary between the LOCOS oxide film and the device region, in the vicinity thereof, and in the bent region in order to prevent leakage current. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5665590U JPH0415860U (en) | 1990-05-30 | 1990-05-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5665590U JPH0415860U (en) | 1990-05-30 | 1990-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0415860U true JPH0415860U (en) | 1992-02-07 |
Family
ID=31580671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5665590U Pending JPH0415860U (en) | 1990-05-30 | 1990-05-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0415860U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118176A (en) * | 2000-10-05 | 2002-04-19 | Nec Corp | Semiconductor device |
-
1990
- 1990-05-30 JP JP5665590U patent/JPH0415860U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118176A (en) * | 2000-10-05 | 2002-04-19 | Nec Corp | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS55130178A (en) | Semiconductor device | |
| JPS57172761A (en) | Semiconductor integrated circuit | |
| JPH0415860U (en) | ||
| JPS6297358A (en) | Resin sealed type semiconductor integrated circuit device | |
| JPS6418239A (en) | Semiconductor integrated circuit device | |
| JPH06283604A (en) | Semiconductor device | |
| JPS58222573A (en) | Semiconductor integrated circuit device | |
| EP0344055A3 (en) | Semiconductor integrated circuit device | |
| JPS6320440U (en) | ||
| JPS59139646A (en) | Semiconductor integrated circuit device | |
| JPS62188275A (en) | Field effect transistor | |
| JPH04199570A (en) | Integrated circuit | |
| JPS6324641A (en) | Semiconductor integrated circuit device | |
| JPH0338878A (en) | Dual gate type insulated gate field effect transistor | |
| JPH0225054A (en) | Master slice lsi | |
| JPH0157822U (en) | ||
| JPH05136268A (en) | Semiconductor integrated circuit | |
| JPH01109746A (en) | Cmos gate array | |
| JPS6211240A (en) | Semiconductor device | |
| JPH02304951A (en) | Master-slice semiconductor integrated circuit | |
| JPH09326439A (en) | Semiconductor device | |
| JPS61197730U (en) | ||
| JPS63182830A (en) | Semiconductor device | |
| JPH02281745A (en) | gate array device | |
| JPS6228452U (en) |