JPH0415928A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a reverse mesa and separate an emitter electrode and base electrodes from each other by a simplified self-alignment process by using the top semiconductor layer of a multilayer structure as a mask and using etching liquid to etch lower semiconductor layers faster than the top semiconductor layer. CONSTITUTION:A second emitter cap layer 10 is etched to form an electrode contact 10a, which is used as a mask in etching. Etching liquid consists of NH4OH, H2O2, and H2O in the ratio of 3:1:50 (volume). The second emitter cap layer on the top used as the mask is not etched by the etching liquid. A cap grade layer 9, a first emitter cap layer 8, a second emitter grade layer 7, an emitter layer 6, and a first emitter grade layer 5 under the second emitter cap layer can be selectively etched and the etching time can be regulated to form a reverse mesa structure 11. An emitter electrode 12 on the electrode contact 10a and base electrodes 13 are formed self-alignedly. A base mesa is formed from part of the base electrodes 13 and a part of a base layer 4 and a collector electrode 14 is formed from a part of a collector layer 3.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a vertical transistor, and aims to provide a method of forming a base electrode separated from an emitter by a simplified self-alignment process. .

A process of forming a multilayer structure consisting of a plurality of semiconductor layers on a semiconductor substrate, a process of patterning the top layer of the multilayer structure to form an electrode contact part, and a process of etching the semiconductor layer below the top layer with the etching rate of the top semiconductor layer. The method of manufacturing a semiconductor device includes the step of etching using an etching solution higher than the etching speed of 1, using the electrode contact portion as a mask, and forming an inverted mesa with a multilayer structure under the electrode contact. In addition, a step of forming a multilayer structure including a first semiconductor layer of one conductivity type, a semiconductor layer of an opposite conductivity type, and a second semiconductor layer of one conductivity type in this order on a semiconductor substrate, and patterning the top layer of the multilayer structure to form an electrode. In the step of forming the contact portion, an etching solution is used in which the etching rate of the semiconductor layer below the top layer is higher than the etching rate of the top semiconductor layer.

A step of etching using the electrode contact portion as a mask to form an inverted mesa with a multilayer structure on the semiconductor layer of the opposite conductivity type below one electrode contact, and forming an electrode on the semiconductor layer of the opposite conductivity type to the electrode contact portion. A semiconductor device manufacturing method includes a step of forming a semiconductor device.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a reduced size transistor.

Heterojunction bipolar transistor (HBT) and resonant tunneling hot electron transistor (RHE)
In manufacturing vertical transistors such as T), the base electrode is formed in a self-aligned manner with respect to the emitter in order to reduce the base resistance. It is desirable that this self-alignment process be simple.

[Conventional technology]

Conventionally, as a method of forming a base electrode in a self-aligned manner with respect to an emitter, 1) a method of forming an insulating film sidewall on the side surface of the emitter and utilizing it;

■A method of forming a dummy emitter of an insulating film and using it ■A method of forming an inverted mesa by taking advantage of the fact that the etching rate in wet etching depends on the surface orientation.

How to use the reverse mesa.

and so on.

However, method (2) requires a process to separate the emitter and base electrode, and method (2) requires a complicated process of first forming an inverted mesa using a dummy emitter and then replacing the dummy emitter with an emitter. Although the method (2) can form a reverse mesa on a certain plane orientation, it becomes a forward mesa on a plane deviated by 90 degrees from that direction, which generally has problems such as inconvenience in separating the emitter and base electrodes.

[Problems to be Solved by the Invention] In view of the above-mentioned problems, an object of the present invention is to provide a method that can perform separation between emitter and base electrodes by a simplified self-alignment process.

[Means to solve the problem]

The above problem is that the semiconductor substrate 1 has a plurality of semiconductor layers 2 to 10
a step of patterning the uppermost layer 10 of the multilayer structure to form an electrode contact portion 10a; etching using an etching solution higher than the etching rate of the layer and using the electrode contact portion 10a as a mask;
An inverted mesa 11 having a multilayer structure is provided under the electrode contact portion 10a.
The problem is solved by a method of manufacturing a semiconductor device that forms a semiconductor device.

Further, the semiconductor substrate 1 is provided with a first one conductivity type semiconductor layer 3, an opposite conductivity type semiconductor layer 4. A step of forming a multilayer structure including a second one-conductivity type semiconductor layer 6 in this order, a step of patterning the uppermost layer IO of the multilayer structure to form an electrode contact portion 10a, and a semiconductor layer below the uppermost layer 10. The electrode contact portion 10 is etched using an etching solution whose etching rate is higher than that of the semiconductor layer of the uppermost layer 10.
etching is performed using mask 10a to form an inverted mesa 11 having a multilayer structure below the electrode contact portion 10a and on the semiconductor layer 4 of the opposite conductivity type; and evaporating metal from above to form the electrode contact portion. First electrode 1 on 10a
2. The problem is solved by a method for manufacturing a semiconductor device, which includes a step of forming a second electrode 13 on the semiconductor layer 4 of the opposite conductivity type.

[Effect]

In the present invention, several layers of the multilayer structure below are selectively etched using the uppermost semiconductor layer 10 of the multilayer structure as a mask. That is, an etching solution is used in which the etching rate of the semiconductor layer below the top layer is higher than the etching rate of the top semiconductor layer.

By using such an etching solution, an inverted mesa 11 having a multilayer structure can be formed under the electrode contact portion 10a.

Also, using this reverse mesa, metal is deposited from above,
A second electrode 13 is formed on the semiconductor layer 4 having a conductivity type opposite to that of the first electrode 12 on the electrode contact portion 10a. When the first electrode 12 is used as an emitter electrode and the second electrode 13 is used as a base electrode, the base electrode 13 can be formed separated from the emitter by a very small distance. Furthermore, in this case, the emitter electrode 12 is simultaneously connected to the base electrode 13.
can also be formed, which simplifies the process.

〔Example〕

FIGS. 1(a) to (f) are cross-sectional views for explaining the process of the example.
This is an example of applying the method of the present invention to the production of T.

The following description will be made with reference to these figures.

Referring to FIG. 1(a), on a GaAs substrate 1, a collector contact layer 2, a collector layer 3. Base layer 4. First emitter grade layer5.
Emitter layer 6. Second emitter grade layer7. First emitter cap layer 8. Cap grade layer 9. A second emitter cap layer 1o is epitaxially grown in this order.

The composition and thickness of each layer are as follows.

Code Layer name Composition Dose (cm) Thickness (person) 2, Collector contact layer n”-GaAs 5 XIO” 50
003, Collector layer 1-GaAs or n-GaAs 3 Xl0I62000~5000 4, Base layer p"-GaAs or p"-AIX Ga1-
x As(ni~0-Q,I) > l XIO" 500~10005, first emitter grade layer N-A1. Ga+-, As 5 xlO"
300 (x=0.1~0.3) 6. Emitter layer N-Al0.3 Gao, 7As 5 XIO”
10007, second emitter grade layer N-^lx Ga1-x As 5 ~ 50
xlO'F 300 (X・0.3 ~ 0) 8, First emitter cap layer n''-GaAs 5 XIO'' 50
09, cap grade layer n'' 4n*Ga+-XAs 5~50xlOI
81000 (X・0~0.6) 10, second emitter camp layer n'-1rr, bGao, a As 5xlO"
500 (See FIG. 1(b)) Form a pattern for forming an emitter with photoresist on the second emitter cap layer 1o (not shown) 2 For example, the second emitter cap layer 10 is etched using the etching solution shown below. The electrode contact portion 10a is formed by etching.

H3PO4:H2O2:H2O~1:1:8 (
(volume ratio) Alternatively, the electrode contact portion 10a can also be formed using Ar ion milling.

FIG. 1(c) Using the reference electrode contact portion 10a as a mask, the camber grade layer 9. First emitter cap layer 8. Second emitter grade layer 7. The emitter grade layer 5 of the emitter 1 is selectively etched to form an inverted mesa structure 11.

As the etching solution, a composition of NH4OH:HzO□:HzO=3:1:50 (volume ratio) is used. In this etching solution, the uppermost second emitter cap layer n −1n serves as a mask.
o. 1Gaa. 4As is not etched. Depending on the case, increase the amount of )1.0 to adjust the etching speed to an appropriate level.

Figure 2 shows the etching rate of compound semiconductors using the above etching solution.
745.

Ino. bGao. It shows the relationship between etching depth and aAs etching time.

As can be seen from this figure, with this etching solution, G
aAs+ Alo, IGao. Js is etched but Ino. bGao. 4AS is not etched at all. However, the etching rate of InxGa+-xAs also increases as the In composition becomes less than 0.6.

Therefore, Ino. aGao. If nAs is used as a mask material, the underlying cap grade layer 9. The first emitter camp layer 8, the second emitter grade layer 7, the emitter layer 6, and the first emitter grade layer 5 can be selectively etched. The inverted mesa structure 11 can be formed by adjusting the etching time.

Refer to Fig. 1(d) from the top: 100mm thickness Pri, 1000mm thickness Pt,
Au with a thickness of 2000 to 3000 mm, or Prr with a thickness of 100 mm, and Au with a thickness of 2000 to 3000 mm are deposited in this order. An emitter electrode 12 and a base electrode 13 are formed. The emitter electrode 12 is formed on the electrode contact portion 10a. The base electrode 13 is formed in self-alignment with the electrode contact portion 10a. Since the emitter layer 6 has an inverted mesa structure, it is separated from the base electrode 13. There will be no contact.

In FIG. 1(e), a part of the reference base if Fk 13 and a part of the base layer 4 are etched and removed. Forms a base mesa.

Referring to FIG. 1(f), the collector layer 3 is partially etched to form a recess that exposes the collector contact layer 2, and the AuGe/A
The collector electrode 14 is formed by evaporating layers u (200/3000) in this order.

HBT was produced in this way.

Note that the collector layer and base layer. The method of the present invention can also be applied to a structure in which the stacking order of the emitter layers is reversed and the collector electrode is formed on the electrode contact portion 10a.

Furthermore, the method of the present invention is applicable not only to HBTs but also to other vertical transistors, such as RHETs.

〔Effect of the invention〕

As explained above, according to one aspect of the present invention, etching is performed by using the uppermost layer of an epitaxially grown multilayered semiconductor layer as a mask and using an etching solution having a different etching rate for each layer. A multilayered inverted mesa can be formed.

Further, the emitter and base electrode can be separated using the reverse mesa. According to the present invention, there is no need for a special process for separating the emitter and base electrodes, and the emitter and base electrodes can be formed at the same time, which greatly simplifies the process.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) are cross-sectional views for explaining the process of the embodiment. FIG. 2 is a diagram showing the etching rate of compound semiconductors. In the figure, ■ is a semiconductor substrate, which is a GaAs substrate. 2 is the collector contact layer. 3 is a collector layer, which is a first semiconductor layer of one conductivity type. 4 is a base layer, which is a semiconductor layer of an opposite conductivity type. 5 is a first emitter grade layer 6 is an emitter layer, and a second - conductivity type semiconductor layer 7 is a second emitter grade layer. 8 is a first emitter cap layer 9 is a cap grade layer. 10 is a second emitter cap layer, which is the uppermost layer 10a.
is the electrode contact part. 11 is a reverse mesa. 12 is an emitter electrode, which is a first electrode. 13 is a base electrode and is a second electrode. 14 is the collector electrode (e) (f)
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Claims (1)

[Claims] [1] A plurality of semiconductor layers (2 to 10 layers) on a semiconductor substrate (1)
), and patterning the uppermost layer (10) of the multilayer structure to form electrode contact portions (
10a), using an etching solution in which the etching rate of the semiconductor layer under the top layer (10) is higher than the etching rate of the semiconductor layer of the top layer (10),
a step of etching using the electrode contact portion (10a) as a mask, and forming an inverted mesa (11) with a multilayer structure under the electrode contact portion (10a). . [2] First one-conductivity type semiconductor layer (3) on semiconductor substrate (1)
), a step of forming a multilayer structure including an opposite conductivity type semiconductor layer (4), and a second one conductivity type semiconductor layer (6) in this order, and patterning the uppermost layer (10) of the multilayer structure to form an electrode contact portion. (10a) and the etching rate of the semiconductor layer below the top layer (10)
Etching is performed using an etching solution higher than the etching rate of the semiconductor layer in step 10), using the electrode contact portion (10a) as a mask.
a) forming an inverted mesa (11) with a multilayer structure below and on the semiconductor layer (4) of the opposite conductivity type; and depositing metal from above to form the electrode contact portion (10a).
) on the first electrode (12), the opposite conductivity type semiconductor layer (
4) A method for manufacturing a semiconductor device, comprising the step of forming a second electrode (13) thereon.