JPH0416498U - - Google Patents
Info
- Publication number
- JPH0416498U JPH0416498U JP5651790U JP5651790U JPH0416498U JP H0416498 U JPH0416498 U JP H0416498U JP 5651790 U JP5651790 U JP 5651790U JP 5651790 U JP5651790 U JP 5651790U JP H0416498 U JPH0416498 U JP H0416498U
- Authority
- JP
- Japan
- Prior art keywords
- image
- address signal
- reduction device
- write
- pixel data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Studio Circuits (AREA)
- Editing Of Facsimile Originals (AREA)
Description
第１図は本考案に係る画像縮小装置の一実施例
を示すブロツク図、第２図は本発明の画像縮小装
置を含む画像処理装置を示すブロツク図、第３図
は第１図の画像縮小装置の動作を示すタイムチヤ
ート、第４図は本考案におけるＤＲＡＭ内の格納
例を示す図である。
１……ＣＰＵ、３……画像データ制御部、５…
…画像メモリ部（ＶＲＡＭ）、７……フレームバ
ツフア部（ＤＲＡＭ）、９……表示装置、１１…
…制御回路、１３……ライト信号間引き手段（横
方向加算回路）、１５……アドレス作成手段手段
（縦方向加算回路）、１７……ライト信号間引き
手段（ＯＲ回路）、１９……アドレス作成手段手
段（アドレス制御回路）。
FIG. 1 is a block diagram showing an embodiment of the image reduction device according to the present invention, FIG. 2 is a block diagram showing an image processing device including the image reduction device of the invention, and FIG. 3 is the image reduction device shown in FIG. 1. FIG. 4 is a time chart showing the operation of the device, and is a diagram showing an example of storage in the DRAM according to the present invention. 1...CPU, 3...Image data control unit, 5...
...Image memory unit (VRAM), 7...Frame buffer unit (DRAM), 9...Display device, 11...
...Control circuit, 13...Write signal thinning means (horizontal addition circuit), 15...Address creation means (vertical addition circuit), 17...Write signal thinning means (OR circuit), 19...Address creation means means (address control circuit).
Claims (1)
行（ロウ）および列（カラム）で与えるダイナミ
ツクＲＡＭであつて、ロウアドレス信号のラツチ
中に入力されたカラムアドレス信号およびライト
信号によつて画像の横方向画素データをカラムア
ドレスに順次連続的に格納するダイナミツクＲＡ
Ｍと、 前記各行の所定の画素周期で前記ライト信号を
間引いて前記ダイナミツクＲＡＭに加えるライト
信号間引き手段と、 前記行を移るときに所定の行周期で間引いて作
成した前記ロウアドレス信号を前記ダイナミツク
ＲＡＭに加えるアドレス作成手段と、 を具備することを特徴とする画像縮小装置。[Claims for Utility Model Registration] A dynamic RAM that provides addresses for storing vertical and horizontal pixel data of an image in rows and columns, and that uses a column address signal and a column address signal input while the row address signal is latched. Dynamic RA that sequentially and continuously stores horizontal pixel data of an image in column addresses using write signals.
M; write signal thinning means for thinning out the write signal at a predetermined pixel period in each row and adding it to the dynamic RAM; An image reduction device comprising: address creation means added to a RAM; and an image reduction device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5651790U JPH0416498U (en) | 1990-05-31 | 1990-05-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5651790U JPH0416498U (en) | 1990-05-31 | 1990-05-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0416498U true JPH0416498U (en) | 1992-02-10 |
Family
ID=31580415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5651790U Pending JPH0416498U (en) | 1990-05-31 | 1990-05-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0416498U (en) |
-
1990
- 1990-05-31 JP JP5651790U patent/JPH0416498U/ja active Pending
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