JPH04165471A - Parts arrangement design support system - Google Patents
Parts arrangement design support systemInfo
- Publication number
- JPH04165471A JPH04165471A JP2291528A JP29152890A JPH04165471A JP H04165471 A JPH04165471 A JP H04165471A JP 2291528 A JP2291528 A JP 2291528A JP 29152890 A JP29152890 A JP 29152890A JP H04165471 A JPH04165471 A JP H04165471A
- Authority
- JP
- Japan
- Prior art keywords
- line
- length
- signal line
- designated
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は部品配置設計支援方式に関し、特に電子機器の
プリント配線板の部品配置設計支援に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a component placement design support system, and particularly to component placement design support for printed wiring boards of electronic devices.
従来の部品配置設計支援方式は、部品間の仮想配線長を
短くするように配置するか、部品間においたカットライ
ンを横切る配線の数が少なくなるように配置していた。In conventional component placement design support systems, parts are arranged so that the virtual wiring length between them is shortened, or the number of wirings that cross cut lines placed between parts is reduced.
上述した従来の部品配置設計支援方式は、配線処理で分
岐配線を許した場合に、主軸線に対する各ロードピンの
分岐線長が一定にならない欠点と、配線処理を行った時
、配線長が指定線長以内になるかどうか保証されない欠
点がある。The conventional component placement design support method described above has the disadvantage that when branch wiring is allowed in wiring processing, the branch line length of each load pin with respect to the main axis line is not constant, and when wiring processing is performed, the wiring length is not the same as the specified line. There is a drawback that there is no guarantee that it will be within the long term.
本発明の部品配置設計支援方式は、プリント配線板の部
品配置設計支援方式において、前記プリント配線板に搭
載される部品及び部品間信号線等の論理接続情報を格納
した論理接続情報記憶手段と;前記信号線及びその主軸
線長1分岐線長を指定する信号線指定手段と;前記信号
線指定手段を介して指定された信号線に接続する部品を
前記論理接続情報記憶手段を参照して求め、この指定さ
れた信号線に接続する部品のなかからソースビンを持つ
部品と最終ロードピンを持つ部品とを選択し配置可能領
域に配置指定し、この2つの部品の前記ソースビン及び
前記最終ロードピン間を主軸線として前記信号線指定手
段を介して指定された主軸線長以内で配線指定し、前記
主軸線の両隣に前記信号線指定手段を介して指定された
分岐線長だけ離れた仮線を設定し、前記指定された信号
線に接続する未配置の部品をそのロードピンが前記仮線
上に載る様に配置指定し、これらの部品の配置情報を出
力する部品配置処理手段とを有している。A component placement design support method of the present invention is a component placement design support method for a printed wiring board, comprising: a logical connection information storage means storing logical connection information of components mounted on the printed wiring board and signal lines between the components; signal line designation means for designating the signal line and its main axis length and one branch line length; determining a component to be connected to the signal line designated via the signal line designation means with reference to the logical connection information storage means; , select a component with a source bin and a component with a final load pin from among the components connected to the specified signal line, designate the component to be placed in the placeable area, and set the main axis between the source bin and the final load pin of these two components. Wiring is specified as a line within the main axis line length specified via the signal line specifying means, and temporary lines are set on both sides of the main axis line separated by the branch line length specified via the signal line specifying means. , a component placement processing means for specifying the placement of unplaced components connected to the specified signal line so that their load pins are placed on the temporary line, and outputting placement information of these components.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のブロック図である。本実施
例の部品配置設計支援方式は、論理接続情報ファイル1
0からの論理接続情報を格納する論理接続情報記憶部1
と、クロック信弓等のクリティカルな信号線を指定する
信号線指定部3と、主軸線の長さを指定する主軸線指定
部4と、分岐線の長さを指定する分岐線指定部5と、ク
リティカルな信号線に接続する部品名を記憶する信号線
接続部品名記憶部6と、クリティカルな信号線に接続す
る部品数をカウントする信号線接続部品数カウンタ7と
、配置処理済の部品数をカウントする処理済部品数カウ
ンタ8と、配線可能領域内の部品配置状況を格納する配
線領域マツプ記憶部9と、上記各部を制御して指定され
たクリティカルな信号線に対する部品配置を行い部品配
置情報を部品配置情報ファイル11に出力し部品配置不
能時のエラー情報をエラーファイル12に出力する部品
配置処理部2とを有している。FIG. 1 is a block diagram of one embodiment of the present invention. The component placement design support method of this embodiment is based on the logical connection information file 1.
Logical connection information storage unit 1 that stores logical connection information starting from 0
, a signal line specification section 3 for specifying a critical signal line such as a clock signal line, a main axis line specification section 4 for specifying the length of the main axis line, and a branch line specification section 5 for specifying the length of the branch line. , a signal line connection component name storage unit 6 that stores the names of components connected to critical signal lines, a signal line connection component number counter 7 that counts the number of components connected to critical signal lines, and a number of components that have been placed. a processed parts counter 8 for counting the number of parts, a wiring area map storage part 9 for storing the parts placement status within the routeable area, and a wiring area map storage section 9 for storing the parts placement status within the routeable area; It has a component placement processing section 2 that outputs information to a component placement information file 11 and outputs error information when a component placement is impossible to an error file 12.
次に、動作を説明する。第2図(a)、(b)にフロー
チャートを、第3図に部品の配置例を示す。Next, the operation will be explained. Flowcharts are shown in FIGS. 2(a) and 2(b), and an example of arrangement of parts is shown in FIG.
部品配置処理部2の制御により以下の処理を行う。信号
線指定部3により分岐線長を一定にしたいクロック信号
等の信号線Wαを指定する(ステップ81)。論理接続
情報記憶部1の論理接続情報から信号線αに接続する部
品を抽出し、それぞれをaiとし、信号線接続部品名記
憶部6に格納する(ステップS2)。部品aiの中から
信号線αのソースビンを持つ部品Pと信号線αの最終ロ
ードピンを持つ部品Qを選択する(ステップS3)。部
品aiの全個数をカウント値jとして信号線接続部品数
カウンタ7へ設定しておく(ステップ84)。配線領域
マツプ記憶部9の情報に基づいて部品Pと部品Qとを配
線可能領域内に配置す る(ステップS5)。信号線接
続部品数カウンタ7のカウント値jから部品P、Qの2
個分を差し引いておく(ステップS6)。部品Pのソー
スビンと部品Qの最終ロードピンを主軸線指定部4によ
り理論上の遅延計算に基づき指定された線長以内で配線
し、このパターンを主軸線りとする(ステップS7)。The following processing is performed under the control of the component placement processing section 2. The signal line specifying unit 3 specifies a signal line Wα for a clock signal or the like whose branch line length is desired to be constant (step 81). Components connected to the signal line α are extracted from the logical connection information in the logical connection information storage unit 1, each is designated as ai, and stored in the signal line connection component name storage unit 6 (step S2). A component P having a source bin for the signal line α and a component Q having the final load pin for the signal line α are selected from the components ai (step S3). The total number of parts ai is set as a count value j in the signal line connected parts number counter 7 (step 84). Based on the information in the wiring area map storage section 9, parts P and Q are arranged within the wiring possible area (step S5). 2 of parts P and Q from the count value j of the signal line connected parts counter 7
The amount for each item is subtracted (step S6). The source bin of the part P and the final load pin of the part Q are wired within the line length specified by the main axis line specifying section 4 based on the theoretical delay calculation, and this pattern is used as the main axis line (step S7).
主軸線りの両隣に分岐線指定部5により指定された分岐
線長mだけ離れた所に配置のための仮線N1とN2とを
設定する(ステップS8)。Temporary lines N1 and N2 for placement are set on both sides of the main axis line, separated by the branch line length m specified by the branch line specifying section 5 (step S8).
次に、信号線接続部品名記憶部6に格納されている残り
のすべての部品aiについて配置処理を行う。まず、処
理済部品数カウンタ8のカウント値iをII OITに
設定しくステップS9)、配置処理が行なわれるたびに
そのカウント値iに“1”を加算する(ステップ510
)。仮線N。Next, placement processing is performed for all remaining components ai stored in the signal line connection component name storage section 6. First, the count value i of the processed parts counter 8 is set to II OIT (step S9), and "1" is added to the count value i every time placement processing is performed (step S510).
). Temporary line N.
上で部品Pから任意の距離d離れた点を点01とする(
ステップ511)。分岐線により信号線αに継がる部品
aiのロードピンが点o1上に載るように部品atを配
置する(ステップ512)。ステップ812の処理で部
品aiが他の部品と重なるならば(ステップS13のY
ES)、点01を仮線N1上を微小距離Δd離れた位置
に移動させ(ステップ514)、点O□が仮線N1の終
点(部品Q)に行きつくまでステップ812〜ステツプ
S14の処理を繰返す。点01が仮線N、の終点に行き
ついたら(ステップS15のYES)、仮線N2上の部
品Pより距離dだけ離れた点を02としくステップ81
B)、上記と同様に、点02上に部品aiを配置しくス
テップ517)、他の部品と重なるならば(ステップ8
18のYES)、点02を仮線N2の終点に行きつくま
で微小距離Δdずつ移動させながら(ステップ519)
、ステップ817〜ステツプS19の処理を繰り返す。In the above, let the point 01 be an arbitrary distance d away from the part P (
Step 511). The component at is arranged so that the load pin of the component ai, which is connected to the signal line α by a branch line, is placed on the point o1 (step 512). If part ai overlaps with another part in the process of step 812 (Y of step S13)
ES), move the point 01 to a position a minute distance Δd away on the temporary line N1 (step 514), and repeat the processes from step 812 to step S14 until the point O□ reaches the end point (part Q) of the temporary line N1. . When the point 01 reaches the end point of the temporary line N (YES in step S15), set the point 02 on the temporary line N2 from the part P by a distance d in step 81.
B), in the same way as above, place part ai on point 02 (step 517), if it overlaps with another part (step 8
18), while moving the point 02 by a minute distance Δd until it reaches the end point of the temporary line N2 (step 519).
, repeats the processing from step 817 to step S19.
点02が仮線N2の終点に行きついたら(ステップS2
0のYES)、部品atは配置不能としてエラー情報を
出力しエラーファイル12に書込む(ステップ21)。When point 02 reaches the end point of temporary line N2 (step S2
0 (YES), the component at is determined to be unplaceable, and error information is output and written to the error file 12 (step 21).
ステップS13またはステップ818で他の部品と重な
らなかった部品aiに対して、部品配置情報を取出し部
品配置情報ファイル11に書込む(ステップ522)。For parts ai that did not overlap with other parts in step S13 or step 818, component placement information is extracted and written in the component placement information file 11 (step 522).
処理済部品数カウンタ8のカウント値iが信号線接続部
品数カウンタ7のカウント値jの値未満の間、ステップ
810〜ステツプS22の処理を繰返す(ステップ52
3)。While the count value i of the processed parts number counter 8 is less than the count value j of the signal line connected parts number counter 7, the processes from step 810 to step S22 are repeated (step 52
3).
以上説明したように本発明は、信号線名を指定し、接続
する部品の中よりソースピンと最終ロードピンを持つ部
品を配置可能領域中に置き、そのソースピンと最終ロー
ドピンを指定線長で結線した主軸線を設けその主軸線の
両隣の指定分岐線長だけ離れた所に仮線を設けて残りの
部品のロードピンが先の仮線上に載るように部品を配置
することによって、配線長が指定線長以内でかつ主軸線
に対して分岐線長がほぼ一定になるような部品配置情報
を得られる効果がある。As explained above, the present invention specifies a signal line name, places a component having a source pin and a final load pin from among the components to be connected in a placeable area, and connects the source pin and final load pin with a specified line length to a main shaft. The wiring length can be changed to the specified line length by setting a temporary line on both sides of the main axis line and placing a temporary line on both sides of the main axis line, at a distance of the specified branch line length, and placing the components so that the load pins of the remaining components rest on the previous temporary line. It is possible to obtain component placement information such that the branch line length is approximately constant with respect to the main axis.
第1図は本発明の一実施例のブロック図、第2図は本発
明のフローチャート、第3図は本発明による部品の配置
例を示す図である。
1・・・論理接続情報記憶部、2・・・部品配置処理部
、3胃信号線指定部、4・・・主軸線指定部、5・・・
分岐線指定部、6・・・信号線接続部品名記憶部、7・
・・信号線接続部品数カウンタ、8・・・処理済部品数
カウンタ、9・・・配線領域マツプ記憶部、10・・・
論理接続情報ファイル、11・・・部品配置情報ファイ
ル、12・・・エラーファイル。FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flow chart of the present invention, and FIG. 3 is a diagram showing an example of arrangement of parts according to the present invention. DESCRIPTION OF SYMBOLS 1... Logical connection information storage section, 2... Component placement processing section, Trigastric signal line specification section, 4... Main axis line specification section, 5...
Branch line specification section, 6...Signal line connection part name storage section, 7.
... Signal line connected parts number counter, 8... Processed parts number counter, 9... Wiring area map storage section, 10...
Logical connection information file, 11...Component placement information file, 12...Error file.
Claims (1)
記プリント配線板に搭載される部品及び部品間信号線等
の論理接続情報を格納した論理接続情報記憶手段と;前
記信号線及びその主軸線長、分岐線長を指定する信号線
指定手段と;前記信号線指定手段を介して指定された信
号線に接続する部品を前記論理接続情報記憶手段を参照
して求め、この指定された信号線に接続する部品のなか
からソースピンを持つ部品と最終ロードピンを持つ部品
とを選択し配置可能領域に配置指定し、この2つの部品
の前記ソースピン及び前記最終ロードピン間を主軸線と
して前記信号線指定手段を介して指定された主軸線長以
内で配線指定し、前記主軸線の両隣に前記信号線指定手
段を介して指定された分岐線長だけ離れた仮線を設定し
、前記指定された信号線に接続する未配置の部品をその
ロードピンが前記仮線上に載る様に配置指定し、これら
の部品の配置情報を出力する部品配置処理手段とを有す
ることを特徴とする部品配置設計支援方式。In a component placement design support system for a printed wiring board, a logical connection information storage means storing logical connection information such as components mounted on the printed wiring board and signal lines between the components; the signal lines, their main axis line lengths, and branches; a signal line designating means for designating a line length; determining a component to be connected to the signal line designated by the signal line designating means with reference to the logical connection information storage means, and connecting it to the designated signal line; A component having a source pin and a component having a final load pin are selected from among the components and designated to be placed in a placeable area, and the signal line designation means is set as a main axis between the source pin and the final load pin of these two components. Specify the wiring within the specified main axis line length through the signal line specifying means, set temporary lines on both sides of the main axis line separated by the branch line length specified via the signal line specifying means, and connect the specified signal line to the specified signal line. A component placement design support system comprising a component placement processing means for specifying placement of unplaced components to be connected so that their load pins are placed on the temporary line, and outputting placement information of these components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2291528A JP2985278B2 (en) | 1990-10-29 | 1990-10-29 | Component placement design support method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2291528A JP2985278B2 (en) | 1990-10-29 | 1990-10-29 | Component placement design support method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04165471A true JPH04165471A (en) | 1992-06-11 |
| JP2985278B2 JP2985278B2 (en) | 1999-11-29 |
Family
ID=17770072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2291528A Expired - Fee Related JP2985278B2 (en) | 1990-10-29 | 1990-10-29 | Component placement design support method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2985278B2 (en) |
-
1990
- 1990-10-29 JP JP2291528A patent/JP2985278B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2985278B2 (en) | 1999-11-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2536125B2 (en) | Placement processing method | |
| JPH04165471A (en) | Parts arrangement design support system | |
| JP2531084B2 (en) | Parts gap check device | |
| US4837706A (en) | Drawing processing apparatus | |
| JP2528954B2 (en) | Memory access control method | |
| JP2834843B2 (en) | Electronic component mounting device | |
| JPH0245225B2 (en) | ||
| JPH04348830A (en) | Mounting order deciding device | |
| JP3248800B2 (en) | Circuit diagram creation device and circuit diagram creation method | |
| JP3132878B2 (en) | Component mounting method | |
| JPH0523932A (en) | Parts installer | |
| JPS5864562A (en) | Signal processor | |
| JPS62162400A (en) | Method of predetermining order of parts to be mounted | |
| JPH0442571A (en) | Method for arranging integrated circuit element in semiconductor integrated circuit device | |
| JPH02266546A (en) | Arrangement method for integrated circuit element in integrated circuit device | |
| JPH04195373A (en) | Arrangement position determination assisting device | |
| JP2001282860A (en) | Control signal assignment device for control panel | |
| JPH03154363A (en) | Hierarchical arranging and processing system | |
| JPS63100558A (en) | Package selection method | |
| JPH0520392A (en) | LSI system design support device | |
| JPH0785130A (en) | 2 terminal parts mounting drawing change method | |
| JPS60100211A (en) | programmable controller | |
| JPS61128543A (en) | Wiring process | |
| JPS6065339A (en) | program placement device | |
| JPS61288500A (en) | Wire bonding work |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |