JPH04169936A - Signal processor - Google Patents

Abstract

PURPOSE:To efficiently realize the parallel signal processing on a program by providing a program executing part which executes a program selected by a program selecting circuit to store an output signal string in a first or second input/output circuit. CONSTITUTION:In accordance with the program selected by a program selecting circuit 6 which selects one of two kinds of preliminarily prepared program in accordance with a discrimination signal 105, a program executing part 13 reads out an input signal string from internal buffers of a first input/output circuit 7, which takes a signal 108 as the input by a first interrupt input 101 to store it in an internal input buffer and reads out a signal 109 from an internal output buffer to output it from a signal terminal 9, and a second input/output circuit 10 which takes a signal 111 as the input by a second interrupt input 103 to store it in an internal input buffer and reads out a signal 112 from an internal output buffer to output it to a signal output terminal 12. After the processing, the output signal string is stored in internal buffers of first and second input/output circuits 7 and 10. Thus, plural processings are efficiently realized on the program.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal processing processor that can process two signals having different sampling intervals, such as a PCM signal and a digital audio signal, in parallel.

(Prior Art) Conventionally, as methods for processing signals of multiple sampling rates in parallel using a signal processor or the like, there are 1) a method using multiple interrupts, and 2) a method using program control.

In a method using a plurality of interrupts, a prioritized interrupt signal is assigned to each process with a different sampling rate, and the process with each sampling rate is executed using the interrupt signal. Since each sampling rate is different, an interrupt may be input to start processing of a different sampling rate while processing of one rate is being executed. In this case, if the input interrupt has a high priority, the process currently being executed is interrupted, the process corresponding to the interrupt signal is executed, and when the process is completed, the process before the interrupt input is resumed. Furthermore, if the priority is low, interrupt processing is started after the currently executing process ends. In this way, processing depending on the sampling rate can be performed in parallel.

On the other hand, in the method using program control, multi-rate processing is realized by repeatedly executing processing with different sampling rates within one program according to the sampling rate. If the sampling rate ratio is 2:3, this can be achieved by repeating a program that repeats A twice and B three times at a rate that is half the sampling rate of A.

(Problem to be solved by the invention) However, in the method using multiple interrupts, there is a large overhead such as saving the internal state of the processor due to interruption of processing due to high priority interrupts, and real-time processing with strong time constraints There was a need to shorten processing time. Particularly in processors that employ pipeline processing to increase speed, interrupts interrupt the vibe line, resulting in a significant deterioration in computational efficiency.

On the other hand, the method using program control is limited to cases where m and n can each be expressed as an integer, where the ratio of two sampling rates is m:n.

Furthermore, even if each of the numbers can be expressed as an integer, if the least common multiple of m and n is large, the program, processing delay, memory requirements, etc. will become large, which poses a practical problem.

An object of the present invention is to provide a signal processor that can be efficiently implemented on a program even when there are multiple processes in which the ratio of two different sampling rates cannot be expressed as a simple integer ratio.

(Means for Solving the Problems) A signal processor of the present invention includes a frequency dividing circuit that divides a first interrupt input input at a first sampling interval to generate a frequency-divided interrupt signal; a counter circuit that uses a frequency-divided interrupt signal as a reset signal and counts the number of second interrupt inputs input at a second sampling interval within the reset signal interval, and an output of the counter circuit when the reset signal is input; a determination circuit that determines whether the number matches a predetermined number; a program selection circuit that selects one of two programs stored in advance according to the output of the determination circuit; and a first internal input. a buffer and a first internal output buffer, and stores a first input signal in the first internal input buffer in synchronization with the first interrupt input;
a first input/output circuit that outputs the output signal stored in the internal output buffer of the input/output circuit, a second internal input buffer, and a second internal output buffer; a second input/output circuit that stores an input signal in the second internal input buffer and outputs an output signal stored in the second internal output buffer; and the first input/output circuit or the second input/output circuit. an execution unit that executes a program that receives a signal string stored in the first input/output circuit or the second input/output circuit as input, executes a program selected by the program selection circuit, and stores an output signal string in the first input/output circuit or the second input/output circuit; Configured with at least one.

(Operation) The principle of the present invention is shown below. When the ratio of the input and output sampling rates in the system to be realized is expressed as a:m, and when a is a non-integer with respect to an integer value m, n<a< n+
Let n be an integer that is 1. At this time, it is clear that the number of samples input while only m samples are output is n or n+1. Therefore, we prepare in advance a program for when the input/output sampling rate ratio is n:m and a program for n+1:m, so that the number of input samples input while outputting m samples is n. By selecting and executing one of the two programs depending on whether the input/output sampling rate is n+1, it is possible to realize a system in which the input/output sampling rate ratio is a:m.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, which includes a first interrupt input terminal 1, a frequency dividing circuit 2, a second
interrupt input terminal 3, counter circuit 4, judgment circuit 5,
Program selection port #16, first input/output circuit 7, first signal input terminal 8, first signal output terminal 9, second input/output circuit 10, second signal input terminal 11, second signal It is composed of an output terminal 12 and a program execution section 13.

The frequency dividing circuit 2 divides the frequency of the first interrupt input 101 by a predetermined number and outputs the frequency-divided interrupt signal 102. For example, if the number of frequency divisions is M (M is an integer), the frequency dividing circuit 2 outputs the frequency-divided interrupt output once every M inputs of the first interrupt input 101. The counter circuit 4 receives a second interrupt input 10 input at an interval between adjacent inputs of the frequency-divided interrupt signal 102.
A frequency-divided interrupt signal 102 that counts the number of 3.
This can be realized by an up counter that uses the reset signal as the reset signal and the second interrupt input 103 as the counter input. The determination circuit 5 determines whether the output 104 of the counter circuit 4 is equal to a predetermined number based on the frequency-divided interrupt signal 102 input, and outputs a determination signal 105. The program selection circuit 6 selects and outputs one of two types of programs prepared in advance according to the determination signal 105. First input/output circuit R
7 incorporates an internal input buffer and an internal output buffer, inputs a signal 108 from the signal input terminal 8 through the first interrupt input 101, stores it in the internal input buffer, reads out the signal 109 from the internal output buffer, and outputs it to the signal terminal 9. Output from. The second input/output circuit 10 also includes an internal input buffer and an internal output buffer, and receives a signal 111 from the signal input terminal 11 through the second interrupt input 103 and stores it in the internal input buffer, and outputs a signal 112 from the internal output buffer. It is read out and output to the signal output terminal 12. The program execution unit 13 reads the input signal string from the internal buffers of the first input/output circuit 7 and the second input/output circuit 10 according to the program selected by the program selection circuit 6, processes it, and then outputs the output signal string. The first input/output circuit 7
and stored in the internal buffer of the second input/output circuit 10.

It is assumed that the ratio of the sampling rate of the input signal to the sampling rate of the output signal in the signal processor of the embodiment is R, and that M M holds true for R. At this time, the frequency of the first interrupt input 101 is divided by M in the frequency dividing circuit 2, and the number of second interrupt inputs 103 inputted during the M-divided interrupt interval is counted in the counter circuit 4.

This number is either N (N is an integer) or N+1 6 Therefore, when the M-divided interrupt signal 102 is input, the determination circuit 5 checks the output 10 of the counter circuit 4.
It is determined whether 4 is N and a determination signal 105 is output. At the same time, the counter circuit 4 is reset to O. Then, the program selection circuit 6 selects a program as follows and causes the program execution unit 13 to execute it. First, when the determination signal 105 indicates N sample input, the first
Since M samples are input to the internal input buffer of the input/output circuit 7 and N samples are input to the internal input buffer of the second input/output circuit 10, the program selection circuit 6
A program is selected that repeats the process corresponding to the first interrupt process M times and the process corresponding to the second interrupt process N times, and causes the program execution unit 13 to process it. On the other hand, when the determination signal 105 indicates input of N+1 samples, since N+1 samples are input to the built-in buffer of the second person output circuit 10, the program selection circuit 6
A program is selected in which the process corresponding to the first interrupt process is repeated M times, and the process corresponding to the second interrupt process is repeated N+1 times, and is processed in the 10-gram execution 113.

(Effects of the Invention) As explained above, according to the present invention, even when there are processes with two different sampling rates that cannot be expressed by a simple ratio of integers, parallel signal processing can be efficiently realized by a program. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. 1... First interrupt input terminal, 2... Frequency divider circuit,
3... Second interrupt input terminal, 4... Counter circuit, 5... Judgment circuit, 6... 10 gram selection circuit,
7... ■th input/output circuit, 8... first signal input terminal, 9... first signal output terminal, 10... second input/output circuit, 11... second signal input terminal, 12...
second signal output terminal, 13...program execution section;

Claims (1)

[Claims] A frequency dividing circuit that divides a first interrupt input input at a first sampling interval to generate a frequency-divided interrupt signal; a counter circuit that counts the number of second interrupt inputs input at a sampling interval of 2; and a determination circuit that determines whether the output of the counter circuit matches a predetermined number when the reset signal is input. , a program selection circuit that selects one of two programs stored in advance according to the output of the determination circuit, a first internal input buffer, and a first internal output buffer, and the first interrupt a first input/output circuit that stores a first input signal in the first internal input buffer in synchronization with the input and outputs the output signal stored in the first internal output buffer; and a second internal input buffer. and a second internal output buffer;
a second input/output circuit that stores a second input signal in the second internal input buffer and outputs the output signal stored in the second internal output buffer in synchronization with an interrupt input of the first input/output circuit; The signal string stored in the output circuit or the second input/output circuit is input, the program selected by the program selection circuit is executed, and the output signal string is input to the first input/output circuit.
A signal processor comprising at least an input/output circuit or a program execution unit that stores in the second input/output circuit.