JPH0418330B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a clock distribution system, particularly a clock distribution system having a configuration for distributing a free run clock and a stop signal to individual equipment units. Eliminating delay circuits as much as possible from the run clock distribution system to reduce undesirable clock skew;
The present invention also relates to a clock distribution system that enables control such as manual clock control.

(B) Technical Background and Problems Traditionally, in clock distribution systems in data processing equipment, clock signals from a clock oscillator are free-circuited via a clock control circuit.
A run clock is distributed to the individual equipment units, while a stop signal for manual clock control etc. is distributed to each individual equipment unit.

FIG. 1 shows an example of a conventional clock distribution system, in which 1 is a clock oscillator, 2 is a clock control circuit, 3A to 3F are device units,
CLK1 and CLK2 are free run clocks, respectively.
STOP1 to STOP4 are respectively stop signals,
4, 5, 6, 7 are delay circuits (coarse adjustment circuits), 8,
9, 10, . . . represent fine adjustment circuits, respectively.
Further, 23 represents a manual clock control switch.

The transmission time of the free running clock between each equipment unit 3A, 3B, . The phase is finely adjusted by fine adjustment circuits 8, 9, . . . that can adjust the phase.

Under normal operating conditions, the stop signal STOP
1, STOP2... are at logic "1", for example, and in each device unit 3A, 3B,..., the free run clock is kept on by the above-mentioned STOP signal via an AND circuit. Extracted. Furthermore, during manual clock control, one stop signal is issued each time the switch 23 is turned on, as shown in FIG.
The clock CLK and the stop signal STOP are accepted with the same delay and are ANDed to 1.
GATED CLOCK
is extracted as

Conventionally, the configuration is as described above, but if delay circuits 4, 5, 6, 7, etc. are present in the clock transmission route, the clock skew generally becomes large. That is, in general, clock skew is proportional to the amount of delay in a clock transmission route, and the above-mentioned clock skew becomes a major problem, particularly in ultra-high-speed computer systems such as so-called super computers that are being developed recently. For example, in some cases with a 10 ns clock, the time may be about 8 ns.

(C) Object and Structure of the Invention The purpose of the present invention is to solve the above problems, and the clock distribution system of the present invention is such that the clock signal from the clock oscillator is used as a free running clock by the clock control circuit. A stop signal that is distributed to each equipment unit and controls the free run clock is distributed to each equipment unit, and gated in each equipment unit based on the free run clock and the stop signal. - in a clock distribution system in which a clock is generated, said free run clock is distributed between said clock control circuit and said individual equipment units via a fine adjustment circuit capable of adjusting the phase within one machine cycle; The invention is characterized in that the stop signal is distributed between the clock control circuit and the individual device units via a desired delay circuit. This will be explained below with reference to the drawings.

(D) Embodiment of the invention FIG. 3 shows the configuration of an embodiment of the invention, and FIG.
FIG. 5 is an explanatory diagram for explaining the operation of the configuration shown in FIG. 3, and FIG. 5 is an explanatory diagram for explaining the solution related to the configuration shown in FIG. 3.

In Fig. 3, the symbols 1, 2, 3, 6, 7, 8,
9, 10, 11, 12, 13, 14, 15, 1
6, 17, 18, 19, 20, 21, 22, 23
correspond to FIG. 1, respectively. As can be seen from a comparison with FIG. 1, in the case shown in FIG. 3, the delay circuits 4 and 5 that were present in FIG. 1 are not present.

As mentioned above, clock skew is proportional to the amount of delay in the clock transmission route. Therefore, in the case of the present invention, the delay circuits 4 and 5 present in FIG. 1 are omitted as shown in FIG. 3, and the free run clocks CLK1 and CLK2 are operated within one machine cycle as shown in FIG. The signal is distributed to each equipment unit with the minimum amount of delay by only providing phase adjustment. This helps minimize the clock skew mentioned above. On the other hand, the stop signal STOP is
The transmission time should be selected so as to correctly cover one pulse of the free run clock.
This time is selected in delay circuits 6 and 7 depending on each device unit.

Under normal operating conditions, the stop signal STOP
is at logic "1" and each equipment unit 3A, 3
In B,..., free run clock
The fact that CLK is extracted is the same as in the case shown in FIG. However, as mentioned above, the clock skew is sufficiently small. and,
During manual clock control, as shown in FIG. 4, a stop signal is generated to gate, for example, the #4 clock pulse with a predetermined delay to generate a gated clock. Needless to say, the operation time for operating the switch 23 is sufficiently longer than the period of the free run clock, and the clock control circuit 2 operates the free run clock in response to one operation of the switch 23.
Outputs one stop signal with a width that covers one pulse of the run clock.

By configuring as described above, it is possible to obtain a clock distribution system with sufficiently small clock skew with respect to the free run clock CLK, and to provide a gated clock with a predetermined time delay corresponding to manual clock control. However, the related problems will be explained with reference to FIG.

Free run clocks are supplied to each device unit 3A, 3B, . . . as shown in FIG. There may be cases where there are locations that operate in response to. For example, the device unit 3A
There is a case where the device unit 3B operates in response to an odd numbered clock, and the device unit 3B operates in response to an even numbered clock.

In such a case, switch 2 shown in FIG.
3 is operated once, the clock control device 2
are two stop signals as shown in Figure 5 BC.
STOPA and STOPB are respectively issued to cause the gated clock GCLKA to be generated at one location and the gated clock GCLKB to be generated at the other location.

In the clock distribution system, the above figure 5
Although it may be required to operate under manual clock control with the relationship illustrated in ABC, in some cases, the device unit 3 may also be required to operate under manual clock control.
A, 3B, . . . may be operated with a clock that is N times slower than the free run clock. In this case, even if the clock control circuit supplies a clock that is twice as slow as shown in FIG. 5D, for example, in order to operate with a clock that is twice as slow, it is insufficient.
This is because when such a clock is supplied, when the stop signals STOPA and STOPB are issued in response to the operation of the switch 23 as described above, the clock must be gated by the stop signal STOPB. This is because there is no clock.

Taking this into consideration, in order to operate with a clock N times slower as described above, in the case of the present invention, the free run clock is supplied as is, and the stop signals STOPA and STOPB are supplied as free run clocks. A clock gated by a stop signal, as shown in FIGS. 5E and 5F, is sent out once every N cycles of the run clock.
Extract CLKA and CUKB. In this way, for example, the #7 clock gated by the stop signal STOPA and the stop signal
The illustrated #8 clock gated by STOPB has a correct phase lag relationship, and there is no problem.

(E) Effects of the Invention As explained above, according to the present invention, it is possible to suppress undesired clock skew, and it is also possible to correctly perform control using a stop signal.

[Brief explanation of drawings]

Figure 1 shows an example of a conventional clock distribution system.
Fig. 2 is an explanatory diagram explaining its operation, Fig. 3 is an explanatory diagram of an embodiment of the present invention, Fig. 4 is an explanatory diagram explaining its operation, and Fig. 5 is a solution related to the configuration shown in Fig. 3. An explanatory diagram for explaining is shown. In the figure, 1 is a clock oscillator, 2 is a clock control circuit, 3 is a device unit, CLK1 and CLK2 are free run clocks, STOP1 and STOP, respectively.
2 represents a stop signal, 4, 5, 6, 7 are delay circuits, 8, 9, 10, . . . are fine adjustment circuits, and 23 is a manual clock control switch.

Claims (1)

[Scope of Claims] 1. A clock signal from a clock oscillator is distributed to each device unit as a free run clock by a clock control circuit, and a stop signal for controlling the free run clock is distributed to each device unit. In a clock distribution system in which a gated clock is distributed to equipment units and a gated clock is generated in each equipment unit based on the free running clock and the stop signal, a clock control circuit is provided between the clock control circuit and the individual equipment units. The free running clock is distributed through a fine adjustment circuit whose phase can be adjusted to within one machine cycle, and the stop clock is distributed through a desired delay circuit between the clock control circuit and the individual equipment units. What is claimed is: 1. A clock distribution system configured to distribute signals. 2. The clock signal from the clock oscillator is distributed by the clock control circuit to the individual equipment units as a free running clock, and the stop signal for controlling the free running clock is distributed to the respective equipment units, In a clock distribution system in which a gated clock is generated in each equipment unit based on the free run clock and the stop signal, the clock control circuit and the individual equipment unit are connected within one machine cycle. The free running clock is distributed through a fine adjustment circuit capable of adjusting the phase of the clock, and the stop signal is distributed through a desired delay circuit between the clock control circuit and the individual equipment units. The N of the above free run clock is configured as follows:
In generating a low-speed clock that is twice as slow as the free-run clock, the stop signal is
A clock distribution system characterized in that the low-speed clock is generated and distributed once per cycle, and is configured to generate the low-speed clock within the device unit.