JPH04192515A - Manufacture of semiconductor quantum well box - Google Patents
Manufacture of semiconductor quantum well boxInfo
- Publication number
- JPH04192515A JPH04192515A JP32401990A JP32401990A JPH04192515A JP H04192515 A JPH04192515 A JP H04192515A JP 32401990 A JP32401990 A JP 32401990A JP 32401990 A JP32401990 A JP 32401990A JP H04192515 A JPH04192515 A JP H04192515A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- layer
- quantum well
- crystal
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 150000001875 compounds Chemical class 0.000 claims abstract description 45
- 239000013078 crystal Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000013081 microcrystal Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 8
- WGPCGCOKHWGKJJ-UHFFFAOYSA-N sulfanylidenezinc Chemical compound [Zn]=S WGPCGCOKHWGKJJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052984 zinc sulfide Inorganic materials 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 24
- 238000005530 etching Methods 0.000 abstract description 10
- 230000003287 optical effect Effects 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract 3
- 239000000463 material Substances 0.000 description 3
- 125000002524 organometallic group Chemical group 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体量子井戸箱の製造方法に関するものであ
り、特に高性能の半導体レーザ用材料あるいは超高速の
光スィッチや光論理素子などの非線形光学効果をもちい
た光制御素子の実現に必要となる大きな非線形光学定数
を有する材料に関するものである。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor quantum well box, and is particularly concerned with a method for manufacturing a semiconductor quantum well box, and is particularly applicable to nonlinear materials such as high-performance semiconductor laser materials or ultra-high-speed optical switches and optical logic devices. This invention relates to materials with large nonlinear optical constants, which are necessary for realizing light control elements with optical effects.
〈従来の技術〉
半導体量子井戸箱の製造方法として、GaAs(111
)基板上に有機金属気相成長法で三角鐘状のGaAs微
結晶が形成できることが知られている(第37回応用物
理学会関係連合講演会31a −D−6)。これはGa
As (111) B面(As面)、またはA面(Ga
面)上にA I GaAs層を成長させ、ついで条件を
変えて(111) A面(またはB面)で囲まれた一辺
が数10nmの正四面体状GaAs微結晶を成長させ、
さらにその上にAj2−GaAs層を成長させて微結晶
を覆った構造である。<Prior art> As a method for manufacturing a semiconductor quantum well box, GaAs (111
) It is known that triangular bell-shaped GaAs microcrystals can be formed on a substrate by organometallic vapor phase epitaxy (37th Japan Society of Applied Physics Related Conference 31a-D-6). This is Ga
As (111) B surface (As surface) or A surface (Ga surface)
An A I GaAs layer is grown on the (111) A-plane (or B-plane), and then a tetrahedral GaAs microcrystal with a side of several tens of nanometers surrounded by the (111) A-plane (or B-plane) is grown.
Further, an Aj2-GaAs layer is grown thereon to cover the microcrystals.
〈発明が解決しようとする課題〉
しかしながら、従来の半導体量子井戸箱の製缶方法にあ
ってはGaAs(111)基板を用いるのであるが、こ
の場合鏡面状態を保った結晶成長の条件範囲が狭く、ま
た基板面上で特定の結晶軸方向を定めにくい。これは特
に複数の異なる素子を同一基板上へ集積化する際には重
大な欠点となる。<Problem to be solved by the invention> However, in the conventional method for manufacturing semiconductor quantum well boxes, a GaAs (111) substrate is used, but in this case, the range of conditions for crystal growth while maintaining a mirror state is narrow. , and it is difficult to determine a specific crystal axis direction on the substrate surface. This is a serious drawback especially when a plurality of different elements are integrated on the same substrate.
く課題を解決するための手段〉
前記した欠点を解決するため、本発明では化合物半導体
の層状の結晶成長を行なった際、鏡面状の表面状態が得
られる成長条件の範囲が広く、また導波路を形成する際
、光の伝搬方向と結晶軸の方向とを容易に一致させるこ
とのできる化合物半導体の(100)面を使用し、これ
に<110>方向に沿って側面が(111)面である段
差もしくは溝の側部を形成し、この側面上に半導体量子
井戸箱を形成する微結晶の成長を行う。すなわち、本発
明は、第1の化合物半導体からなる半導体基板(100
)面上に閃亜鉛鉱型結晶構造をもつ第2の化合物半導体
の結晶層を成長させる工程と、該第2の化合物半導体の
結晶層の表面にくllO〉方向に沿って、その側面が(
111)面である段差、もしくは溝状の側部を形成する
工程と、前記段差もしくは溝状の側部位置に直接第2の
化合物半導体よりバンドギャップの小さい第3の化合物
半導体の微結晶を成長させる工程又は、前記段差、もし
くは溝状の側部を形成した結晶層表面に、前記閃亜鉛鉱
型結晶構造をもつ第2の化合物半導体と同じ結晶層を、
その層厚が前記段差、もしくは溝状の側部深さよりも小
さくなるように成長させた後、前記段差もしくは溝状の
側部に対応する位置の第2の化合物半導体と同じ、前記
結晶層上に第2の化合物半導体よりバンドギャップの小
さい第3の化合物半導体の微結晶を成長させる工程のい
ずれかと、第3の化合物半導体の微結晶を覆うように第
3の化合物半導体よりもハンドギヤツブの大きな第4の
化合物半導体の結晶層を成長させる工程とからなる半導
体量子井戸箱の製造方法である。Means for Solving the Problems> In order to solve the above-mentioned drawbacks, the present invention provides a wide range of growth conditions for obtaining a mirror-like surface state when layered crystal growth of a compound semiconductor is performed, and also provides a method for forming a waveguide. When forming a compound semiconductor, the (100) plane of the compound semiconductor, which can easily match the direction of light propagation and the direction of the crystal axis, is used, and the sides are (111) planes along the <110> direction. The sides of a certain step or groove are formed and microcrystals are grown on these sides to form a semiconductor quantum well box. That is, the present invention provides a semiconductor substrate (100
) a step of growing a crystal layer of a second compound semiconductor having a zincblende crystal structure on a surface, and a step of growing a crystal layer of a second compound semiconductor having a zincblende crystal structure on a surface thereof, and growing the crystal layer of the second compound semiconductor along the direction
111) A step of forming a step or groove-like side portion that is a plane, and growing microcrystals of a third compound semiconductor having a smaller band gap than the second compound semiconductor directly at the position of the step or groove-like side portion. or a step of forming the same crystal layer as the second compound semiconductor having the zinc blende crystal structure on the surface of the crystal layer on which the step or groove-like side portion is formed;
After growing the layer so that the layer thickness is smaller than the depth of the side portion of the step or groove, the second compound semiconductor is placed on the same layer as the second compound semiconductor at the position corresponding to the side of the step or groove. A step of growing a third compound semiconductor microcrystal having a smaller band gap than the second compound semiconductor, and a step of growing a third compound semiconductor microcrystal having a larger hand gear than the third compound semiconductor so as to cover the third compound semiconductor microcrystal. This is a method for manufacturing a semiconductor quantum well box, which comprises the step of growing a crystal layer of a compound semiconductor in step 4.
く作用〉
本発明は化合物半導体基板(100)面を使用すること
により複数の異なる半導体素子を形成しやすくすると共
に、その化合物半導体の(111)面上へ半導体量子井
戸箱を形成する微結晶の成長を行なうことができる。Effect> The present invention facilitates the formation of a plurality of different semiconductor elements by using the (100) plane of a compound semiconductor substrate, and also uses microcrystals to form a semiconductor quantum well box on the (111) plane of the compound semiconductor. growth can take place.
〈実施例〉 以下、本発明の実施例について説明する。<Example> Examples of the present invention will be described below.
(実施例1)
まず第1の化合物半導体からなるGaAs基板1(10
0)面(0,5度程度のオフ面でも良い)に有機金属気
相成長によりトリメチルガリウム(T?IG)、トリメ
チルアルミニウム
を原料として第2の化合物半導体の結晶層であるA I
GaAs層(2)を厚さ約2μm成長させる。なおA
J組成は0.3とする。このとき成長温度は750〜8
00℃の範囲に設定し、AsとGa, A1のモル比
(V−III比)は20〜50とする。ついでこの表面
の一部をその縁が<011>方向に沿うようにホトレジ
ストで覆う。これをマスクに組成比5:l:1のHgS
O4:HzO□,H20系エツチング液でエツチングす
ると第2図に示すような(111)面が側面に露出した
段差が基板面に形成される。段差3をここでは1μmに
制御した。ホトレジストを除去したのち、この基板を再
度有機金属気相成長装置の炉内に導入し、上記と同様の
条件で第2の化合物半導体と同一組成の結晶層であるA
I GaAs層4を0. 1μm成長させる(第1図
)。これはエツチング処理により、第2の化合物半導体
の結晶層2がエツチング液又は、空気に触れ汚れた表面
となるので、汚れのない第2の化合物半導体の結晶層表
面4を得るためである。従って、結晶層4は省くことも
できる。次に結晶層4の成長後、TMG 、 TMAの
供給を停止し、アルシンのみを流しながら基板温度を7
20℃まで降下する。この状態で再度TMGを10秒間
供給することにより、段差部側面に第3の化合物半導体
の微結晶である正四面体状のGaAs微結晶5が成長す
る。こののち再度昇温し上記と同様な条件において第4
の化合物半導体の結晶であるA I GaAs層6を成
長させる。(Example 1) First, a GaAs substrate 1 (10
A second compound semiconductor crystal layer is formed using trimethylgallium (T?IG) and trimethylaluminum as raw materials by organometallic vapor phase epitaxy on the 0) plane (off-plane of about 0.5 degrees is also acceptable).
A GaAs layer (2) is grown to a thickness of about 2 μm. Furthermore, A
The J composition is set to 0.3. At this time, the growth temperature is 750-8
The temperature is set in the range of 00°C, and the molar ratio of As to Ga and A1 (V-III ratio) is 20 to 50. A portion of this surface is then covered with photoresist so that its edges are along the <011> direction. Using this as a mask, HgS with a composition ratio of 5:l:1
When etching is performed using an O4:HzO□, H20-based etching solution, a step with the (111) plane exposed on the side surface as shown in FIG. 2 is formed on the substrate surface. Here, the height difference 3 was controlled to 1 μm. After removing the photoresist, this substrate was reintroduced into the furnace of the organometallic vapor phase epitaxy apparatus, and a crystal layer having the same composition as the second compound semiconductor was grown under the same conditions as above.
I GaAs layer 4 is 0. Grow to 1 μm (Figure 1). This is to obtain a clean surface 4 of the second compound semiconductor crystal layer since the second compound semiconductor crystal layer 2 comes into contact with the etching solution or air and becomes a dirty surface due to the etching process. Therefore, the crystal layer 4 can also be omitted. Next, after the growth of the crystal layer 4, the supply of TMG and TMA was stopped, and the substrate temperature was raised to 7°C while only arsine was flowing.
The temperature drops to 20°C. By supplying TMG again for 10 seconds in this state, a tetrahedral GaAs microcrystal 5, which is a third compound semiconductor microcrystal, grows on the side surface of the stepped portion. After this, the temperature was raised again and the fourth temperature was raised under the same conditions as above.
An A I GaAs layer 6, which is a compound semiconductor crystal, is grown.
以上により第1図のような断面をもつ量子井戸箱構造が
形成された。この構造はそのまま導波路として使用可能
であり、これに電極を形成して半導体レーザや光スィッ
チなどを作製できる。またこの導波路はアレイ化も容易
であり、また段差部以外の(100)面上に他の素子を
形成し、これと上記素子とを集積化することにも適して
いる。Through the above steps, a quantum well box structure having a cross section as shown in FIG. 1 was formed. This structure can be used as a waveguide as it is, and by forming electrodes on it, semiconductor lasers, optical switches, etc. can be manufactured. Further, this waveguide is easy to form into an array, and is also suitable for forming other elements on the (100) plane other than the step portion and integrating this and the above elements.
以上の工程は一例であって必要に応じて種々変えること
ができる。例えばエツチング液は(111)面のエツチ
ング速度が他の面に比べて遅い組成のものを選べば上記
のものに限らない。結晶成長法も条件を適切に設定すれ
ば分子線エピタキシー法など他の方法も利用できる。ま
たここではGaAs/A I GaAs系について述べ
たが、組成の異なるA I GaAs/A I GaA
sあるいはInP/ InGaAsP系などにおいても
適切なエツチング液を選び、結晶成長条件を設定すれば
同様な量子井戸箱の製造が可能である。The above steps are just examples, and can be modified in various ways as necessary. For example, the etching solution is not limited to those mentioned above, as long as it is selected to have a composition that etches the (111) plane at a slower rate than other planes. Other crystal growth methods such as molecular beam epitaxy can also be used if conditions are set appropriately. In addition, although the GaAs/A I GaAs system has been described here, the A I GaAs/A I GaAs system with a different composition
A similar quantum well box can be manufactured by selecting an appropriate etching solution and setting crystal growth conditions for the S or InP/InGaAsP system.
(実施例2)
第2の実施例を説明する。第4図に示す如くまずGaA
s (100)基板7上に実施例1と同様な条件テA
’jl (yaAsJLf 8を成長させる。この表面
にレジストを塗布し、三光束干渉露光法などの方法を用
いて周期0,25μm程度の縞状のパターンを<011
>・方向に沿って露光し、パターニングする。ついでこ
れをマスクに実施例1と同様なエツチング液でA I
GaAs層表面をエツチングすると第4図のような三角
形状の断面を持つ溝状の構造9が形成できる。このとき
表面には(111)面および(111)面が露出する。(Example 2) A second example will be described. As shown in Figure 4, first GaA
s (100) The same conditions as in Example 1 were applied on the substrate 7.
'jl (yaAsJLf 8) is grown. A resist is applied to this surface, and a striped pattern with a period of about 0.25 μm is formed using a method such as three-beam interference exposure method.
>・Expose and pattern along the direction. Next, using this as a mask, A I was applied using the same etching solution as in Example 1.
When the surface of the GaAs layer is etched, a groove-like structure 9 having a triangular cross section as shown in FIG. 4 can be formed. At this time, the (111) plane and the (111) plane are exposed on the surface.
この表面に第3図に示すようにA I! GaAs層1
0を厚さ50nm成長させる(この層は実施例1と同様
省くことも可能である)。以後は実施例1と同様にGa
As微結晶11を溝側面に形成し、さらにA I Ga
As層12を成長させる。A I GaAs層12を3
μm程度の厚さに成長すると表面をほぼ平坦にすること
ができる。最終的に形成される量子井戸箱構造の断面図
を第3図に示す。この平坦な表面に電極を形成したり、
他の素子を積層することも可能である。以上の工程も実
施例1と同様に種々変えることができる。On this surface, as shown in FIG. 3, A I! GaAs layer 1
0 to a thickness of 50 nm (this layer can be omitted as in Example 1). Thereafter, as in Example 1, Ga
As microcrystals 11 are formed on the side surfaces of the groove, and A I Ga
The As layer 12 is grown. A I GaAs layer 12 3
When grown to a thickness of about μm, the surface can be made almost flat. A cross-sectional view of the finally formed quantum well box structure is shown in FIG. Forming electrodes on this flat surface,
It is also possible to stack other elements. Similar to the first embodiment, the above steps can be modified in various ways.
〈発明の効果〉
本発明によれば、GaAs (100)基板を利用し、
量子井戸箱を含む導波路構造が容易に作製できる。<Effects of the Invention> According to the present invention, using a GaAs (100) substrate,
Waveguide structures including quantum well boxes can be easily fabricated.
このため量子井戸箱の特性を利用した各種光デバイスの
製造が可能になる。This makes it possible to manufacture various optical devices using the characteristics of quantum well boxes.
図面は本発明の実施例を示すものであって、第1図は半
導体量子井戸箱の断面図、第2図は実施例1におけるエ
ツチング加工後の基板の斜視図、第3図は、他の実施態
様を示す半導体量子井戸箱の断面図、第4図は、実施例
2におけるエツチング加工後の基板の斜視図である。
1.7:GaAs基板、2.8rAIGaAs層、4,
10: A I GaAs層、5. 11 :GaA
s1i結晶、6.12: A j! GaAs層
(0’lT)面
第1図
第2図The drawings show embodiments of the present invention, in which FIG. 1 is a sectional view of a semiconductor quantum well box, FIG. 2 is a perspective view of a substrate after etching in embodiment 1, and FIG. 3 is a cross-sectional view of a semiconductor quantum well box. FIG. 4, a sectional view of a semiconductor quantum well box showing an embodiment, is a perspective view of a substrate after etching in Example 2. 1.7: GaAs substrate, 2.8rAIGaAs layer, 4,
10: A I GaAs layer, 5. 11: GaA
s1i crystal, 6.12: A j! GaAs layer (0'lT) surface Figure 1 Figure 2
Claims (1)
)面上に閃亜鉛鉱型結晶構造をもつ第2の化合物半導体
の結晶層を成長させる工程と、該第2の化合物半導体の
結晶層の表面に<110>方向に沿って、その側面が(
111)面である段差、もしくは溝状の側部を形成する
工程と、前記段差もしくは溝状の側部位置に直接第2の
化合物半導体よりバンドギャップの小さい第3の化合物
半導体の微結晶を成長させる工程又は、前記段差、もし
くは溝状の側部を形成した結晶層表面に、前記閃亜鉛鉱
型結晶構造をもつ第2の化合物半導体と同じ結晶層を、
その層厚が前記段差、もしくは溝状の側部深さよりも小
さくなるように成長させた後、前記段差もしくは溝状の
側部に対応する位置の第2の化合物半導体と同じ前記結
晶層上に第2の化合物半導体よりバンドギャップの小さ
い第3の化合物半導体の微結晶を成長させる工程のいず
れかと、第3の化合物半導体の微結晶を覆うように第3
の化合物半導体よりもバンドギヤツプの大きな第4の化
合物半導体の結晶層を成長させる工程とからなる半導体
量子井戸箱の製造方法。(1) A semiconductor substrate made of a first compound semiconductor (100
) a step of growing a crystal layer of a second compound semiconductor having a zincblende crystal structure on a surface, and a step of growing a crystal layer of a second compound semiconductor having a zinc blende crystal structure on a surface thereof, and a side surface of the crystal layer of the second compound semiconductor along the <110> direction.
111) A step of forming a step or groove-like side portion that is a plane, and growing microcrystals of a third compound semiconductor having a smaller band gap than the second compound semiconductor directly at the position of the step or groove-like side portion. or a step of forming the same crystal layer as the second compound semiconductor having the zinc blende crystal structure on the surface of the crystal layer on which the step or groove-like side portion is formed;
After growing the layer so that the layer thickness is smaller than the depth of the side portion of the step or groove, the layer is grown on the same crystal layer as the second compound semiconductor at the position corresponding to the side of the step or groove. A step of growing a third compound semiconductor microcrystal having a smaller band gap than the second compound semiconductor, and a step of growing a third compound semiconductor microcrystal so as to cover the third compound semiconductor microcrystal.
A method for manufacturing a semiconductor quantum well box comprising the step of growing a crystal layer of a fourth compound semiconductor having a larger bandgap than that of the compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32401990A JPH04192515A (en) | 1990-11-27 | 1990-11-27 | Manufacture of semiconductor quantum well box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32401990A JPH04192515A (en) | 1990-11-27 | 1990-11-27 | Manufacture of semiconductor quantum well box |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04192515A true JPH04192515A (en) | 1992-07-10 |
Family
ID=18161237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32401990A Pending JPH04192515A (en) | 1990-11-27 | 1990-11-27 | Manufacture of semiconductor quantum well box |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04192515A (en) |
-
1990
- 1990-11-27 JP JP32401990A patent/JPH04192515A/en active Pending
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