JPH04192594A - Printed-wiring board - Google Patents

Abstract

PURPOSE:To prevent the generation of a discontinuity in a circuit pattern by a method wherein the conductor width of the circuit pattern which is situated at the part of the boundary between a solder resist and a plate layer is specified. CONSTITUTION:With a solder resist 3 applied on the surface of a board 1 in such a way as to cover one part of a circuit pattern 2 to be formed on the surface of the board 1, the conductor width, which is situated at the part of the boundary between the resist 3 and a plated layer 4 of the printed-wiring board with the layer 4 provided on the surface, which is not covered with the resist 3, of the pattern 2 is set in 0.3mm or wider. By setting the conductor width in 0.3mm or wider in such a way, the conductor width situated at the part of the boundary is wide and it is eliminated that a stress due to a difference between the thermal expansion coefficients of the board and the pattern 2 is concentrated on the narrow width. Thereby, the generation of a disconnection, which is caused by the difference between the thermal expansion coefficients, in the circuit pattern 2 is reduced.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a printed wiring board in which a part of the surface of a circuit pattern is plated with nickel plating or the like.

[Traditional sister technique]

In a printed wiring board formed by providing a circuit pattern 2 consisting of circuit lines 10, lands 11, etc. by etching copper foil on the surface of a substrate l made of a laminate or the like, one of the circuit patterns 2 is A solder resist 3 is applied to the surface of the substrate 1 so as to cover the solder resist 3, and a plating layer 4 such as nickel plating is provided on the surface of the circuit pattern 2 that is not covered by the solder resist 3. FIG. 5 shows an example, in which a solder resist 3 is printed and applied so as to cover the surface of the circuit line IO except for the land 11 portion of the circuit pattern 2, and the land 1
The plating layer 4 is formed on the part 1 (in the figure, the parts where the solder resist 3 is applied are shown with dots, and the parts where the plating layer 4 is applied are shown with crossed diagonal lines).
.

[Problem to be solved by the invention]

However, if the plating layer 4 is provided on a part of the circuit pattern 2 as described above, there will be a difference in the coefficient of thermal expansion between the part of the circuit pattern 2 where the plating layer 4 is provided and the part where the plating layer 4 is not provided. As a result, the boundary between the solder resist 3 and the plating layer 4 (indicated by the arrow A in FIG. 5)
There was a problem that wire breakage occurred due to the difference in thermal expansion coefficient. In particular, the boundary between the solder resist 3 and the plating layer 4 has a narrow circuit line 10 (the circuit width is generally 0.
2 mm or less), this disconnection is likely to occur because stress due to the difference in thermal expansion coefficients will be concentrated in a narrow width. Moreover, this disconnection is likely to occur when the thickness of the plating layer 4 is 3 μm or more. The present invention has been made in view of the above points, and it is an object of the present invention to provide a printed wiring board that can prevent disconnections from occurring in the circuit pattern at the boundary between the solder resist and the plating layer. It is.

[Means to solve the problem]

In the present invention, a solder resist 3 is applied to the surface of the substrate I so as to cover a part of the circuit pattern 2 formed on the surface of the substrate I, and a plating layer 4 is applied to the surface of the circuit pattern 2 that is not covered with the solder resist 3. This printed wiring board is characterized in that the circuit width dimension of the circuit pattern 2 at the boundary between the solder resist 3 and the plating layer 4 is set to 0.3 mm or more.

[For use]

In the present invention, the circuit width dimension of the circuit pattern 2 at the boundary between the solder resist 3 and the plating layer 4 is set to 0.3 mm.
Because of the above setting, the circuit width at this boundary portion is wide, and the stress due to the difference in thermal expansion coefficients is not concentrated in a narrow width.

【Example】

The present invention will be explained in detail below with reference to Examples. The board 1 is made of a resin laminate or the like, and a circuit pattern 2 formed by circuit lines IO, lands 11, etc. is provided on its surface by etching metal foil such as copper foil. . FIG. 1 shows an embodiment of the present invention, in which a connecting portion 12 between a circular land 11 with a large diameter and a circuit line 10 with a small width is connected to the runt 11 side with a wide width and the circuit line 10 side with a narrow width. It is formed into a fan shape. Then, a solder resist 3 is printed and applied on the surface of the board 1 so as to cover the circuit line 10 except for the land 11, and as shown in FIG. Plating layer 4 is applied by applying nickel plating or gold plating to the surface.
form. At this time, the solder resist 3 is printed so that the boundary line between the solder resist 3 and the plating layer 4 is located above the connection portion 12. Therefore, even if the width of the circuit line IO in the circuit pattern 2 is 0.2 mm or less, the width W of the circuit pattern 2 at the boundary between the solder resist 3 and the plating layer 4 can be reduced by 0.3 mm by the connecting portion 12.
It is something that can be set to 1 mm or more. By setting the width W of the circuit pattern 2 at the boundary between the solder resist 3 and the plating layer 4 to 0.3 mm or more in this way, the circuit width at the boundary between the solder resist 3 and the plating layer 4 can be widened. As a result, the stress due to the difference in thermal expansion coefficient between the part with the plating layer 4 and the part without the plating layer 4 is not concentrated in a narrow width part, and as a result, the coefficient of thermal expansion can be reduced. This makes it possible to reduce the occurrence of wire breakage due to the difference. If the width W of the circuit pattern 2 at the boundary between the solder resist 3 and the plating layer 4 is less than 0.3 m, the effect of reducing the occurrence of wire breakage cannot be sufficiently obtained. In the embodiment shown in FIG. 2, the circuit line 10 of circuit pattern 2 is set to 0.
．． The width of the circuit pattern 2 at the boundary between the solder resist 3 and the plating layer 4 is 0.3 m or more depending on the width of the circuit line IO.
It is set to be greater than or equal to m. In the embodiment shown in FIG. 3, the circuit line IO of the circuit pattern 2 is formed with a terminal portion 13 provided at the end, and this circuit line IO
A wide portion 14 is provided at the boundary between the solder resist 3 and the plating layer 4. This wide portion I4 is set to have a width of 0.3 mm or more, and depending on the width of this wide portion 14, the width W of the circuit pattern 2 at the boundary between the solder resist 3 and the plating layer 4 is set to 0.3 mm or more. It is designed to be set at .3 mm or more.

【Effect of the invention】

As described above, in the present invention, the circuit width dimension of the circuit pattern at the boundary between the solder resist and the plating layer is set to 0.
Since it is set to 3 mm or more, the circuit width at the boundary between the solder resist and the plating layer becomes wider, and stress due to the difference in thermal expansion coefficient between the part with the plating layer and the part without the plating layer increases. This eliminates the concentration of wires in narrow width portions, thereby reducing the occurrence of wire breaks due to differences in thermal expansion coefficients.

[Brief explanation of the drawing]

Fig. 1 is a plan view of a part of one embodiment of the present invention, Fig. 2 is a plan view of a part of another embodiment of the above, and Fig. 3 is a plan view of a part of still another embodiment of the same. FIG. 4 is a sectional view of the same as above, and FIG. 5 is a plan view of a part of the conventional example. l is the board, 2 is the circuit pattern, 3 is the solder resist,
4 is the plating layer

Claims (1)

[Claims] (1) In a printed wiring board in which a solder resist is applied to the surface of the board so as to cover a part of the circuit pattern formed on the surface of the board, and a plating layer is provided on the surface of the circuit pattern that is not covered with the solder resist, A printed wiring board characterized in that the circuit width of the circuit pattern at the boundary between the solder resist and the plating layer is set to 0.3 mm or more.