JPH04196381A - Multi-chip semiconductor device and its manufacturing method - Google Patents

Multi-chip semiconductor device and its manufacturing method

Info

Publication number
JPH04196381A
JPH04196381A JP2322769A JP32276990A JPH04196381A JP H04196381 A JPH04196381 A JP H04196381A JP 2322769 A JP2322769 A JP 2322769A JP 32276990 A JP32276990 A JP 32276990A JP H04196381 A JPH04196381 A JP H04196381A
Authority
JP
Japan
Prior art keywords
elements
flexible printed
semiconductor device
manufacturing
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2322769A
Other languages
Japanese (ja)
Inventor
Katsuhiro Arakawa
勝広 荒川
Kazuo Hirota
和夫 廣田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2322769A priority Critical patent/JPH04196381A/en
Publication of JPH04196381A publication Critical patent/JPH04196381A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To enable semiconductor elements to be enhanced in mounting density by a method wherein semiconductor elements are mounted on a flexible printed board, and the board is bent to enable the semiconductor elements to overlap each other. CONSTITUTION:Semiconductor elements 2 are mounted on a flexible printed board 1 provided with a wiring and input-output terminals 3 are provided to the board 1, and then the board 1 is bent over. In this manufacturing method, the semiconductor elements 2 are connected to the flexible printed board 1 previously provided with a wiring and the input-output terminals 3, and a coating is provided onto the elements 2 and the element joints for the protection of the elements. By this setup, a multichip semiconductor device can be enhanced in mounting density without enlarging a module in size.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマルチチップ半導体装置及びその製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-chip semiconductor device and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

従来の装置は、特開昭６３−１８６４５７号に記載のよ
うに素子を積層し素子相互の配線接続を行う構成となっ
ていた。しかし、この技術では、装置製造時の歩止まり
と製造の簡便さに関する配慮が十分ではなかった。The conventional device has a structure in which elements are stacked and interconnections are made between the elements as described in Japanese Patent Laid-Open No. 186457/1983. However, with this technology, sufficient consideration has not been given to the yield rate and ease of manufacturing during device manufacturing.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明の目的は、複数の半導体素子の実装密度を向上さ
せることにある。An object of the present invention is to improve the packaging density of a plurality of semiconductor elements.

本発明の他の目的は、前記半導体装置に記憶素子を用い
ることにより装置の記憶容量を増やすことにある。Another object of the present invention is to increase the memory capacity of the semiconductor device by using a memory element in the semiconductor device.

本発明の他の目的は、前記半導体装置を容易に製造する
ことにある。Another object of the present invention is to easily manufacture the semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、フレキシブルプリント板に
半導体素子を実装し、その基板を折り曲げて素子を重ね
合わせるように配置したものである。上記他の目的を達
成するために、半導体素子に記憶素子を用いたものであ
る。In order to achieve the above object, semiconductor elements are mounted on a flexible printed board, the board is bent, and the elements are arranged so as to be overlapped. In order to achieve the other objects mentioned above, a memory element is used as a semiconductor element.

上記他の目的を達成するために、フレキシブルプリント
板と素子の接続は基板は折り曲げない状態で行うもので
ある。In order to achieve the other objects mentioned above, the flexible printed board and the element are connected without bending the board.

〔作用〕[Effect]

フレキシブルプリント板へ素子を実装するだけなので、
容易に製造できる。All you have to do is mount the device on a flexible printed board.
Easy to manufacture.

〔実施例〕〔Example〕

以下、本発明の一実施例を第１図、第２図及び第３図に
より説明する。An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.

第１図（ａ）、（ｂ）は本発明の一実施例を示す斜視図
である。第１図（ａ）は（ｂ）の展開図である。本発明
の半導体装置は、配線が施されたフレキシブルプリント
板１上に半導体素子２を接続し入出力端子３を設けたあ
と、フレキシブルプリント板１を折り曲げ、第１図（ｂ
）に示すような実装密度を高めた構造としている。FIGS. 1(a) and 1(b) are perspective views showing one embodiment of the present invention. FIG. 1(a) is a developed view of FIG. 1(b). The semiconductor device of the present invention is manufactured by connecting a semiconductor element 2 to a flexible printed board 1 provided with wiring and providing input/output terminals 3, and then bending the flexible printed board 1, as shown in FIG.
) The structure has a high packaging density as shown in the figure below.

第２図は本発明の製造法の１実施例を示す。まず、配線
と外部との入出力端子が施されたフレキシブルプリント
板１に半導体素子２を接続する。FIG. 2 shows an embodiment of the manufacturing method of the present invention. First, the semiconductor element 2 is connected to the flexible printed board 1 provided with wiring and external input/output terminals.

つぎに、その素子の保護のためにコーティングを素子及
び素子接続部に施こす。さらに、たとえば破線部でおり
曲げ第２図（ｂ）を得る。必要により、全体をコーティ
ングする・ なお、本実施例の半導体素子に記憶素子を用いることに
より高い記憶容量を得ることができる。Next, a coating is applied to the element and the element connection portion to protect the element. Further, for example, the broken line portion is bent to obtain the shape shown in FIG. 2(b). If necessary, the entire structure is coated. Note that by using a memory element in the semiconductor element of this example, a high memory capacity can be obtained.

第３図は半導体素子２に放熱板５を設けた一実施例を示
す斜視図である。半導体素子に放熱板を設けることによ
り、発熱する素子にも本発明が適用できる。FIG. 3 is a perspective view showing an embodiment in which a heat sink 5 is provided on the semiconductor element 2. As shown in FIG. The present invention can also be applied to elements that generate heat by providing a heat sink on the semiconductor element.

〔発明の効果〕〔Effect of the invention〕

半導体素子の数を増やすことによりモジュールの大きさ
をそれほど変える必要なく高い実装密度を得ることがで
きる。By increasing the number of semiconductor elements, high packaging density can be obtained without changing the size of the module much.

また、本発明の製造方法によれば、複雑な位置合わせが
いらず高密度実装が容易に得られ技術的効果が大である
。Furthermore, according to the manufacturing method of the present invention, high-density packaging can be easily achieved without requiring complicated positioning, which has great technical effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第３図は本発明の構造を示す斜視図、第２図は
本発明製造方法を示す斜視図である。 １・・フレキシブルプリント板。 ２・・・半導体素子、　　　３・・・入出力端子、案　
１　図 （戊） （ｂ） 第　２　図 （ｃＬ）1 and 3 are perspective views showing the structure of the present invention, and FIG. 2 is a perspective view showing the manufacturing method of the present invention. 1.Flexible printed board. 2... Semiconductor element, 3... Input/output terminal, proposal
1 Figure (戊) (b) Figure 2 (cL)

Claims (3)

【特許請求の範囲】[Claims] １．複数の半導体素子が実装されたフレキシブルプリン
ト板を折り曲げた構造としたことを特徴とするマルチチ
ップ半導体装置。1. A multi-chip semiconductor device characterized by having a structure in which a flexible printed board on which a plurality of semiconductor elements are mounted is bent. ２．前記半導体素子に記憶素子を用いたことを特徴とす
る請求項第１項記載の半導体装置。2. 2. The semiconductor device according to claim 1, wherein a memory element is used as the semiconductor element. ３．複数の半導体素子を実装したフレキシブルプリント
板を素子の実装されていない箇所で曲げ、次いで素子保
護膜を施す行程を含むことを特徴とするマルチチップ半
導体装置の製造方法。3. 1. A method for manufacturing a multi-chip semiconductor device, comprising the steps of: bending a flexible printed board on which a plurality of semiconductor elements are mounted at locations where no elements are mounted; and then applying an element protection film.
JP2322769A 1990-11-28 1990-11-28 Multi-chip semiconductor device and its manufacturing method Pending JPH04196381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2322769A JPH04196381A (en) 1990-11-28 1990-11-28 Multi-chip semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2322769A JPH04196381A (en) 1990-11-28 1990-11-28 Multi-chip semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH04196381A true JPH04196381A (en) 1992-07-16

Family

ID=18147441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2322769A Pending JPH04196381A (en) 1990-11-28 1990-11-28 Multi-chip semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH04196381A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001075971A1 (en) * 2000-03-31 2001-10-11 Hitachi, Ltd. Semiconductor device and its manufacturing method
JP2007103554A (en) * 2005-10-03 2007-04-19 Rohm Co Ltd Hybrid integrated circuit device and manufacturing method thereof
JP2011159802A (en) * 2010-02-01 2011-08-18 Nec Corp Semiconductor device, three-dimensional integrated circuit, and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001075971A1 (en) * 2000-03-31 2001-10-11 Hitachi, Ltd. Semiconductor device and its manufacturing method
JP2007103554A (en) * 2005-10-03 2007-04-19 Rohm Co Ltd Hybrid integrated circuit device and manufacturing method thereof
JP2011159802A (en) * 2010-02-01 2011-08-18 Nec Corp Semiconductor device, three-dimensional integrated circuit, and method for manufacturing the same

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