JPH0419834U - - Google Patents
Info
- Publication number
- JPH0419834U JPH0419834U JP5737090U JP5737090U JPH0419834U JP H0419834 U JPH0419834 U JP H0419834U JP 5737090 U JP5737090 U JP 5737090U JP 5737090 U JP5737090 U JP 5737090U JP H0419834 U JPH0419834 U JP H0419834U
- Authority
- JP
- Japan
- Prior art keywords
- frequency division
- terminal
- output
- data
- down counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の奇数分周回路の構成ブロツク
図、第２図は本考案の奇数分周回路の動作を説明
するタイムチヤート、第３図は従来の奇数分周回
路の構成ブロツク図、第４図は従来の奇数分周回
路の動作を説明するためのタイムチヤートである
。
１……クロツク発生器、２……バツフア、３…
…分周数設定部、４……第一のダウンカウンタ、
５……第２のダウンカウンタ、６……Ｄ形フリツ
プフロツプ。
FIG. 1 is a block diagram of the structure of the odd frequency divider circuit of the present invention, FIG. 2 is a time chart explaining the operation of the odd frequency divider circuit of the present invention, and FIG. 3 is a block diagram of the conventional odd frequency divider circuit. FIG. 4 is a time chart for explaining the operation of a conventional odd number frequency divider circuit. 1...Clock generator, 2...Buffer, 3...
...Dividing number setting section, 4...First down counter,
5...Second down counter, 6...D type flip-flop.
Claims (1)
設定部と、 この分周数設定部から前記分周データがデータ
端子に入力され、基本クロツクがクロツク端子に
入力される第１のダウンカウンタと、 前記分周数設定部から前記分周データがデータ
端子に入力され、前記基本クロツクの反転信号が
クロツク端子に入力される第２のダウンカウンタ
と、 前記第１のダウンカウンタからの出力によりセ
ツトされ、前記第２のダウンカウンタからの出力
によりリセツトされるＤ形フリツプフロツプとを
備え、 Ｄ形フリツプフロツプのＱ端子出力を前記第１
のダウンカウンタのロード端子に与え、Ｑ端子出
力を前記第２のダウンカウンタのロード端子に与
えるとともに、このＱ端子出力を分周出力として
得ることを特徴とする奇数分周回路。[Scope of Claim for Utility Model Registration] A frequency division number setting section for setting frequency division data that determines the frequency division number; The frequency division data is inputted from the frequency division number setting section to the data terminal, and the basic clock is input to the clock terminal. a first down counter to which the frequency division data from the frequency division number setting section is input to the data terminal, and a second down counter to which the inverted signal of the basic clock is input to the clock terminal; a D-type flip-flop that is set by the output from the first down counter and reset by the output from the second down-counter;
An odd number frequency dividing circuit characterized in that the Q terminal output is applied to a load terminal of a second down counter, and the Q terminal output is obtained as a frequency divided output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5737090U JPH0419834U (en) | 1990-05-31 | 1990-05-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5737090U JPH0419834U (en) | 1990-05-31 | 1990-05-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0419834U true JPH0419834U (en) | 1992-02-19 |
Family
ID=31582013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5737090U Pending JPH0419834U (en) | 1990-05-31 | 1990-05-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0419834U (en) |
-
1990
- 1990-05-31 JP JP5737090U patent/JPH0419834U/ja active Pending
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